Timing Analysis Method for Digital Circuit Design and System Thereof

1. A timing analysis method for a digital circuit design, comprising: obtaining an integrated circuit design, wherein the integrated circuit design is operated in a plurality of operating modes; respectively generating a plurality of extracted timing models according to the operating modes of the integrated circuit design, wherein each of the extracted timing models comprises a none on-chip variation part and an on-chip variation part; integrating the extracted timing models corresponding to the operating modes into a none on-chip variation extracted timing model and an on-chip variation extracted timing model, wherein the on-chip variation part of the operating modes is not considered when the none on-chip variation extracted timing model is generated; and simulating a timing checking of the integrated circuit design according to the none on-chip variation extracted timing model and the on-chip variation extracted timing model, wherein the none on-chip variation part comprises a logic gate delay analysis information set and a timing arc verification information set, the on-chip variation part comprises a chip setup derating information and a chip hold derating information, wherein the logic gate delay analysis information set comprises at least one combinational cell delay message, at least one sequential cell delay message and a pulse width message, and the logic gate delay analysis information set and the timing arc verification information set do not comprise a signal setup margin factor and a signal hold margin factor related to an on-chip variation, and wherein the integrated circuit design is provided for manufacturing an integrated circuit.

2. The timing analysis method for the digital circuit design as claimed in claim 1 , wherein the chip setup derating information comprises a chip setup margin message to consider the on-chip variation, the chip hold derating information set comprises a chip hold margin message to consider the on-chip variation, and the chip setup margin message and the chip hold margin message respectively use different on-chip variation derating factors to implement supplement and derating of the on-chip variation.

3. The timing analysis method for the digital circuit design as claimed in claim 1 , wherein the step of respectively generating the extracted timing models comprises: not to consider the chip setup derating information and the chip hold derating information when the none on-chip variation extracted timing model is generated.

4. The timing analysis method for the digital circuit design as claimed in claim 1 , wherein the step of respectively generating the extracted timing models comprises: generating the extracted timing models by adopting a global on-chip variation supplement derating technique.

5. The timing analysis method for the digital circuit design as claimed in claim 1 , wherein the step of simulating the timing checking of the integrated circuit design comprises: loading the none on-chip variation extracted timing model and the on-chip variation extracted timing model to an auto-place-route tool to perform a static timing analysis process.

6. The timing analysis method for the digital circuit design as claimed in claim 5 , wherein the step of simulating the timing checking of the integrated circuit design comprises: loading the signal setup margin factor and the signal hold margin factor related to the on-chip variation to the auto-place-route tool to perform the static timing analysis process.

7. The timing analysis method for the digital circuit design as claimed in claim 1 , wherein the extracted timing models are generated by adopting a same library corner.

8. A computer readable storage media, configured to store a computer program, wherein the computer program is loaded to a computer system to execute the timing analysis method for the digital circuit design as claimed in the claim 1 .

9. A timing analysis system for a digital circuit design, adapted to a computer device, the timing analysis system comprises: a transmission module, configured to receive an integrated circuit design, where the integrated circuit design is operated in a plurality of operating modes; a timing extraction module, configured to respectively generate a plurality of extracted timing models according to the operating modes of the integrated circuit design, wherein each of the extracted timing models comprises a none on-chip variation part and an on-chip variation part; a timing model integration module, configured to integrate the extracted timing models corresponding to the operating modes into a none on-chip variation extracted timing model and an on-chip variation extracted timing model, wherein the on-chip variation part of the operating modes is not considered when the none on-chip variation extracted timing model is generated; and a timing analysis module, simulating a timing checking of the integrated circuit design according to the none on-chip variation extracted timing model and the on-chip variation extracted timing model, wherein the none on-chip variation part comprises a logic gate delay analysis information set and a timing arc verification information set, the on-chip variation part comprises a chip setup derating information and a chip hold derating information, wherein the logic gate delay analysis information set comprises at least one combinational cell delay message, at least one sequential cell delay message and a pulse width message, and the logic gate delay analysis information set and the timing arc verification information set do not comprise a signal setup margin factor and a signal hold margin factor related to an on-chip variation, and wherein the integrated circuit design is provided for manufacturing an integrated circuit.

10. The timing analysis system for the digital circuit design as claimed in claim 9 , wherein the chip setup derating information comprises a chip input setup margin message to consider the on-chip variation, the chip hold derating information set comprises a chip hold margin message to consider the on-chip variation, and the chip input setup margin message and the chip hold margin message respectively use different on-chip variation derating factors.

11. The timing analysis system for the digital circuit design as claimed in claim 9 , wherein the timing extraction module does not consider the chip setup derating information and the chip hold derating information when the none on-chip variation extracted timing model is generated.

12. The timing analysis system for the digital circuit design as claimed in claim 9 , wherein the timing extraction module adopts a global on-chip variation supplement derating technique to generate the extracted timing models.

13. The timing analysis system for the digital circuit design as claimed in claim 9 , wherein the timing analysis module loads the none on-chip variation extracted timing model and the on-chip variation extracted timing model to an auto-place-route tool to perform a static timing analysis process.

14. The timing analysis system for the digital circuit design as claimed in claim 13 , wherein the timing analysis module loads the signal setup margin factor and the signal hold margin factor related to the on-chip variation to the auto-place-route tool to perform the static timing analysis process.

15. The timing analysis system for the digital circuit design as claimed in claim 9 , wherein the timing extraction module generates the extracted timing models by adopting a same library corner.