Graphical View and Debug for Coverage-Point Negative Hint

1. A method for verifying a design of an integrated circuit, the method comprising: generating a hardware description language representative of the design; generating a symbolic variable for at least each of a first plurality of variables of the design, wherein each symbolic variable is a symbolic representation having a random value; performing a symbolic simulation run; capturing symbolic properties associated with the first plurality of symbolic variables over a number of simulation cycles, wherein each symbolic property represents a symbolic expression associated with one of the symbolic variables at a particular point in time; and displaying the captured symbolic properties in a form of a directed graph comprising a plurality of nodes, wherein each node represents a symbolic variable of a different one of the first plurality of symbolic variables.

2. The method of claim 1 wherein the directed graph displays a network of paths each showing a propagating direction of a symbolic variable through the path.

3. The method of claim 2 wherein the network of paths is displayed concurrently with an associated portion of design, testbench, test or graph based stimulus to the symbolic simulation run.

4. The method of claim 1 wherein the directed graph comprises a plurality of shapes.

5. The method of claim 1 wherein the directed graph comprises a plurality of colors.

6. The method of claim 1 further comprising displaying at least some of the variables in the plurality of variables that transition at a substantially same time along a horizontal or vertical direction.

7. The method of claim 1 further comprising annotating the directed-graph with values of the first plurality of variables resulting from the simulation run.

8. The method of claim 7 further comprising: specifying a target coverage; and displaying values of each the first plurality of variables or paths of the directed graph required to achieve the specified target coverage.

9. The method of claim 8 further comprising displaying a range of values at one or more nodes of the graph that each node may take in addition to the value the node did take and the required values to achieve the specific target coverage.

10. The method of claim 8 further comprising: selecting a node associated with the design; coloring fanin and fanout of nets associated with the selected node; and highlighting code in the hardware description language or directed graph associated with the selected node.

11. A non-transitory computer-readable medium storing computer-executable code which when execute by a processor of a computer system configures the processor for verifying a design of an integrated circuit, the non-transitory computer-readable medium comprising: code for generating a hardware description language representative of the design; code for generating a symbolic variable for at least each of a first plurality of variables of the design, wherein each symbolic variable is a symbolic representation having a random value; code for performing a symbolic simulation run; code for capturing symbolic properties associated with the first plurality of symbolic variables over a number of simulation cycles, wherein each symbolic property represents a symbolic expression associated with one of the symbolic variables at a particular point in time; and code for displaying the captured symbolic properties in a form of a directed graph comprising a plurality of nodes, wherein each node represents a symbolic variable of a different one of the first plurality of symbolic variables.

12. The non-transitory computer-readable medium of claim 11 wherein the directed graph displays a network of paths each showing a propagating direction of a symbolic variable through the path.

13. The non-transitory computer-readable medium of claim 12 wherein the network of paths is displayed concurrently with an associated portion of the design.

14. The non-transitory computer-readable medium of claim 11 wherein the directed graph comprises a plurality of shapes.

15. The non-transitory computer-readable medium of claim 11 wherein the directed graph comprises a plurality of colors.

16. The non-transitory computer-readable medium of claim 11 further comprising code for displaying at least some of the variables in the plurality of variables that transition at a substantially same time along a horizontal or vertical direction.

17. The non-transitory computer-readable medium of claim 11 further comprising code for annotating the directed-graph with values of the first plurality of variables resulting from the simulation run.

18. The non-transitory computer-readable medium of claim 17 further comprising: code for specifying a target coverage; and code for displaying values of each the first plurality of variables required to achieve the specified target coverage.

19. The non-transitory computer-readable medium of claim 18 further comprising code for displaying a range of values the node may node may take in addition to the value the node did take and the required value.

20. The non-transitory computer-readable medium of claim 18 further comprising: code for selecting a node associated with the design; code for coloring fanin and fanout of nets associated with the selected node; and code for highlighting code in the hardware description language associated with the selected node.