System and Method for Providing Operating System Independent Error Control in a Computing Device

1. A method for providing operating system independent error control in computing devices, the method comprising: defining with a reliability, availability and serviceability (RAS) controller a first memory region configured to store information about correctable errors and a second memory region configured to store information about uncorrectable errors; receiving an error indication at the RAS controller indicating whether an error is a correctable error or an uncorrectable error; determining with the RAS controller whether the received error indication indicates the error is a correctable error; and in response to the determination, if the received error indication indicates the error is a correctable error, writing with the RAS controller information about the correctable error to the first memory region and not to the second memory region, and if the received error indication indicates the error is an uncorrectable error, writing with the RAS controller information about the uncorrectable error to the second memory region and not to the first memory region and sending an interrupt request from the RAS controller to an operating system executing on a processor; and polling the first memory region to determine whether there is a correctable error to handle.

2. The method of claim 1 , wherein the RAS controller comprises a second processor separate from the processor executing the operating system.

3. The method of claim 1 , further comprising: communicating a location of the first and second memory regions to an operating system and communicating a polling instruction associated with the first memory region.

4. The method of claim 3 , wherein polling the first memory region is performed in accordance with the polling instruction.

5. The method of claim 3 , wherein communicating the location of the first and second memory regions to the operating system further comprises: writing with the RAS controller the address of the first and second memory regions to a firmware table accessed by the operating system.

6. The method of claim 1 , further comprising: translating the received error into a standard hardware error format.

7. The method of claim 6 , wherein the standard hardware error format comprises a generic hardware error source (GHES) format.

8. The method of claim 1 , further comprising: receiving at the RAS controller an error acknowledgement indicating an error associated with the information in the first memory region or the second memory region has been handled.

9. The method of claim 8 , further comprising: receiving a second error indication at the RAS controller, the second error indication being received before the error acknowledgement is received; and writing information about the second error indication to a buffer.

10. The method of claim 9 , further comprising: writing with the RAS controller information about the second error indication from the buffer to the first memory region or second memory region in response to the received error acknowledgement.

11. A system for providing operating system independent error control, the system comprising: a system on chip (SoC) comprising a processing device executing an operating system and a reliability, availability and serviceability (RAS) controller coupled to the processing device, the RAS controller configured to: define a first memory region configured to store information about correctable errors, define a second memory region configured to store information about uncorrectable errors, receive an error indication indicating whether an error is a correctable error or an uncorrectable error, determine whether the received error indication indicates the error is a correctable error, and in response to the determination, if the received error indication indicates the error is a correctable error, write information about the correctable error to the first memory region and not to the second memory region, and if the received error indication indicates the error is an uncorrectable error, write information about the uncorrectable error to the second memory region and not to the first memory region and send an interrupt request to the operating system, and the operating system is configured to poll the first memory region to determine whether there is a correctable error to handle.

12. The system of claim 11 , wherein the RAS controller comprises a second processing device separate from the processing device executing the operating system.

13. The system of claim 11 , wherein the RAS controller is configured to: communicate a location of the first and second memory regions to the operating system and communicate a polling instruction associated with the first memory region.

14. The system of claim 13 , wherein the operating system is configured to: poll the first memory region in accordance with the polling instruction.

15. The system of claim 13 , wherein the RAS controller is configured to communicate the location of the first and second memory regions to the operating system by: writing the address of the first and second memory regions to a firmware table accessed by the operating system.

16. The system of claim 11 , wherein the RAS controller is configured to: translate the received error into a standard hardware error format.

17. The system of claim 16 , wherein the standard hardware error format comprises a generic hardware error source (GHES) format.

18. The system of claim 11 , wherein the RAS controller is configured to: receive an error acknowledgement from the operating system indicating an error associated with the information in the first memory region or the second memory region has been handled by the operating system.

19. The system of claim 18 , wherein the RAS controller is configured to: receive a second error indication, the second error indication being received before the error acknowledgement is received; and write information about the second error indication to a buffer in communication with the RAS controller.

20. The system of claim 19 , wherein the RAS controller is configured to: write information about the second error indication from the buffer to the first memory region or second memory region in response to the received error acknowledgement.

21. A computer program stored in a non-transitory memory and executable by a processor for providing operating system independent error control, the computer program comprising logic configured to: define a first memory region configured to store information about correctable errors; define a second memory region configured to store information about uncorrectable errors; receive an error indication at a controller indicating whether an error is a correctable error or an uncorrectable error; determine whether the received error indication indicates the error is a correctable error; and in response to the determination, if the received error indication indicates the error is a correctable error, write information about the correctable error to the first memory region and not to the second memory region, and if the received error indication indicates the error is an uncorrectable error, write information about the uncorrectable error to the second memory region and not to the first memory region and send an interrupt request to an operating system executing on a processor, and poll the first memory region to determine whether there is a correctable error to handle.

22. The computer program of claim 21 , wherein the controller comprises a second processor separate from the processor executing the operating system.

23. The computer program of claim 21 , wherein the logic is further configured to: communicate a location of the first and second memory regions to an operating system and communicate a polling instruction associated with the first memory region.

24. The computer program of claim 23 , wherein the logic is further configured to: poll the first memory region in accordance with the polling instruction.

25. The computer program of claim 23 , wherein the logic configured to communicate the location of the first and second memory regions to the operating system comprises logic configured to: write the address of the first and second memory regions to a firmware table accessed by the operating system.

26. A system for providing operating system independent error control in computing devices, the system comprising: means for defining a first memory region configured to store information about correctable errors; means for defining a second memory region configured to store information about uncorrectable errors; means for receiving an error indication at a controller indicating whether an error is a correctable error or an uncorrectable error; means for determining whether the received error indication indicates the error is a correctable error; and in response to the determination, if the received error indication indicates the error is a correctable error, means for writing information about the correctable error to the first memory region and not to the second memory region, and if the received error indication indicates the error is an uncorrectable error, means for writing information about the uncorrectable error to the second memory region and not to the first memory region and means for sending an interrupt request to an operating system executing on a processor, and means for polling the first memory region to determine whether there is a correctable error to handle.

27. The system of claim 26 , wherein the controller comprises a second processor separate from the processor executing the operating system.

28. The system of claim 26 , further comprising: means for communicating a location of the first and second memory regions to an operating system and means for communicating a polling instruction associated with the first memory region.

29. The system of claim 28 , wherein the means for polling the first memory region is configured to poll the first memory region in accordance with the polling instruction.

30. The system of claim 28 , wherein the means for communicating the location of the first and second memory regions to the operating system further comprises: means for writing the address of the first and second memory regions to a firmware table accessed by the operating system.