Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A control method of a system-on-chip including a multi-core processor, the control method comprising: detecting a rate of runnable tasks to be performed in the multi-core processor and a driving voltage or a driving clock of the multi-core processor; determining whether a variation of the rate of the runnable tasks, sampled from a first time point to a current time point, and a variation of the driving voltage or the driving clock, sampled from a second time point to the current time, satisfy a hotplug condition; and plugging in or out at least one core included in the multi-core processor when the rate of the runnable tasks and the driving voltage or the driving clock each satisfy the hotplug condition.
A method for managing power in a system-on-chip (SoC) with a multi-core processor involves monitoring the rate of tasks waiting to be executed and the processor's voltage or clock speed. The system determines if changes in task rate and voltage/clock speed, observed over time, meet predefined "hotplug" conditions. If these conditions are met, the system dynamically enables ("plugs in") or disables ("plugs out") one or more cores within the multi-core processor to optimize power consumption based on the workload.
2. The control method as set forth in claim 1 , wherein a sampling operation of detecting the rate of the runnable tasks and a sampling operation of detecting a driving voltage or a driving clock in the multi-core processor are performed at the same time.
This power management method for a multi-core system-on-chip (as described in claim 1) ensures that the monitoring of the runnable task rate and the monitoring of the driving voltage or clock speed of the multi-core processor occur simultaneously. This synchronous sampling allows for more accurate and responsive power management decisions.
3. The control method as set forth in claim 1 , wherein the driving voltage or the driving clock is calculated with reference to a frequency of a driving clock or a level of a driving voltage provided to the multi-core processor.
In this multi-core SoC power management method (described in claim 1), the driving voltage or clock speed is determined by referencing the frequency of the clock or the voltage level supplied to the multi-core processor. This ensures that the power management decisions are based on the actual operating parameters of the processor.
4. The control method as set forth in claim 1 , wherein in the determining operation, a hotplug condition for the rate of the runnable tasks corresponds to a case where the number of the tasks sampled two or more times for a first cumulative period from the first time to the current time is continuously maintained to be greater or smaller than the number of cores of the multi-core processor that are in an on-line status.
Within the hotplug condition determination of claim 1, the criteria for task rate hotplug events is defined as follows: The number of runnable tasks, sampled at least twice over a cumulative period, remains consistently above or below the number of active (online) cores in the multi-core processor. This persistent state triggers core hotplugging.
5. The control method as set forth in claim 4 , wherein a hotplug-out condition corresponds to a case where the number of the tasks sampled for the first cumulative period is greater than the number of the cores of the multi-core processor that are in the on-line status, and a hotplug-in condition corresponds to a case where the number of the tasks sampled for the first cumulative period is smaller than the number of the cores of the multi-core processor that are in the on-line status.
Continuing from claim 4, the hotplug conditions are further defined: A "hotplug-out" event (disabling a core) is triggered when the sampled task rate remains *above* the number of active cores. Conversely, a "hotplug-in" event (enabling a core) is triggered when the sampled task rate remains *below* the number of active cores. The sampling occurs over the specified first cumulative period from claim 4.
6. The control method as set forth in claim 1 , wherein in the determining operation, a hotplug condition for the driving voltage or the driving clock corresponds to a case where the driving voltage or the driving clock sampled two or more times for a second cumulative period from the second time to the current time is continuously maintained to be greater than or smaller than a reference usage rate.
In the power management method for a multi-core SoC described in claim 1, the "hotplug" condition related to voltage/clock speed involves continuously monitoring samples of these parameters over a second cumulative period. A hotplug event is triggered if the sampled voltage or clock speed consistently exceeds or falls below a predefined reference usage rate during that period.
7. The control method as set forth in claim 6 , wherein a hotplug-in condition corresponds to a case where the driving voltage or the driving clock sampled for the second cumulative period is higher than a first reference value, and a hotplug-out condition corresponds to a case where the driving voltage or the driving clock sampled for the second cumulative period is lower than a second reference value lower than the first reference value.
Building upon claim 6, a "hotplug-in" event (enabling a core, potentially increasing voltage/clock) happens when the voltage or clock speed, sampled across the second cumulative period, is greater than a first reference value. A "hotplug-out" event (disabling a core, potentially decreasing voltage/clock) happens when the sampled voltage or clock speed is less than a second reference value, which is lower than the first.
8. The control method as set forth in claim 1 , wherein in the determination operation, a current power status of the multi-core processor is not changed when the hotplug condition is not satisfied.
Expanding on the multi-core SoC power management method of claim 1, the system ensures that if the "hotplug" conditions (based on task rate and voltage/clock speed) are *not* met, the current power state of the multi-core processor remains unchanged. This prevents unnecessary core state transitions and ensures stability.
9. A system-on-chip comprising: a multi-core processor including a plurality of cores; and a working memory into which an operating system driven by the multi-core processor is loaded and in which a run queue corresponding to each of the cores is established, wherein the operating system includes a kernel adapted to control a hotplug operation of the multi-core processor, and the kernel determines when to execute the hotplug operation on each of the plurality of cores of the multi-core processor by using a result obtained by sampling a runnable task rate and a driving voltage and a driving clock of the multi-core processor, wherein the kernel is configured to determine to plug in or out at least one core, of the plurity of cores, when the runnable task rate changes.
A system-on-chip (SoC) includes a multi-core processor and working memory. The memory stores an operating system that runs on the processor. Each core has its own run queue. The OS kernel controls core "hotplugging" (enabling/disabling cores). The kernel samples the rate of runnable tasks and the processor's voltage/clock speed. The kernel uses these samples to decide when to hotplug cores. The kernel is configured to plug in or plug out at least one core of the plurality of cores, when the runnable task rate changes.
10. The system-on-chip as set forth in claim 9 , wherein the driving voltage or the driving clock of the multi-core processor is sampled using a frequency of a driving clock or a level of a driving voltage provided to the multi-core processor.
As described in claim 9, the system-on-chip (SoC) determines the driving voltage or clock speed of the multi-core processor by sampling the frequency of the driving clock signal or the voltage level provided to the processor. This measurement is used for hotplug decisions in the core power management strategy.
11. The system-on-chip as set forth in claim 9 , wherein the run queue includes a queue corresponding to each of the plurality of cores of the multi-core processor.
In the system-on-chip (SoC) described in claim 9, each core of the multi-core processor has its own, dedicated run queue in the working memory. This allows the operating system's kernel to track tasks independently for each core when managing power through hotplugging.
12. The system-on-chip as set forth in claim 9 , wherein the kernel monitors the number of tasks loaded into the run queue and includes a scheduler adapted to perform task migration.
As described in claim 9, the kernel of the system-on-chip's operating system monitors the number of tasks in the run queues. It also includes a scheduler which can migrate tasks between the different cores. This task migration enables the power management system to balance workloads effectively to avoid unnecessary core activation.
13. The system-on-chip as set forth in claim 12 , wherein the kernel includes a CPU governor adapted to monitor or control the driving voltage or the driving clock of the multi-core processor.
Continuing from claim 12, the kernel of the system-on-chip (SoC) also includes a CPU governor. This governor monitors and controls the driving voltage or the driving clock speed of the multi-core processor. This control allows the kernel to fine-tune the processor's performance and power consumption, complementing the core hotplugging mechanism.
14. The system-on-chip as set forth in claim 9 , wherein the multi-core processor is a heterogeneous multi-core processor in which the driving voltage or the driving clock varies in units of clusters, and the kernel performs the hotplug operation in units of the clusters.
Extending the description of claim 9, if the multi-core processor within the system-on-chip (SoC) is a *heterogeneous* multi-core processor (with cores grouped into clusters having independent voltage/clock controls), the kernel performs the hotplug operations at the cluster level. This allows finer-grained power management than core-by-core control in this specific architecture.
15. The system-on-chip as set forth in claim 9 , further comprising: a performance controller adapted to perform the hotplug operation of the multi-core processor by hardware according to the control of the kernel.
Adding to the system-on-chip (SoC) described in claim 9, a hardware-based performance controller can perform core hotplug operations *directly*, under the control of the operating system's kernel. The kernel makes the decisions, and the hardware controller executes them, providing a faster response time for power management adjustments.
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August 29, 2017
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