Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An information processing apparatus comprising: a first controller circuit that is controlled by a first operating system and that outputs a waiting instruction waiting persistently until a response is transmitted from a control target; and a second controller circuit that is controlled by a second operating system different from the first operating system, that converts the waiting instruction outputted from the first controller circuit into a periodic instruction waiting periodically until a response is transmitted from the control target, and that outputs the periodic instruction to the control target.
An information processing apparatus has two controllers. The first controller, managed by a first operating system, sends a persistent "wait" instruction, halting until it receives a response from a control target. The second controller, using a different operating system, intercepts this persistent wait instruction and converts it into a periodic "wait" instruction. This second controller then sends the periodic wait instruction to the control target, effectively polling the target instead of waiting indefinitely. This allows the first controller to resume processing instead of being blocked.
2. The information processing apparatus according to claim 1 , further comprising: a shared memory that is connected to the first controller circuit and the second controller circuit and that stores the waiting instruction outputted from the first controller circuit, wherein the second controller circuit reads out the waiting instruction stored in the shared memory, and converts the waiting instruction into the periodic instruction.
The information processing apparatus described previously includes a shared memory accessible to both controllers. The first controller writes its persistent "wait" instruction to this shared memory. The second controller reads the wait instruction from the shared memory. The second controller then converts the persistent wait instruction into a periodic "wait" instruction and sends the periodic wait instruction to the control target. This shared memory architecture facilitates communication between the two controllers using different operating systems.
3. The information processing apparatus according to claim 2 , wherein the first controller circuit stores a termination instruction in the shared memory, the termination instruction being an instruction to terminate the periodic instruction and being supplied due to a restart performed after an abnormal termination of the first operating system, and wherein the second controller circuit stops the periodic instruction on the basis of the termination instruction obtained from the shared memory.
The information processing apparatus from the shared memory description has a mechanism for stopping the periodic "wait" instructions. If the first operating system crashes and restarts, the first controller writes a "termination instruction" to the shared memory. This instruction signals that the periodic waiting should stop. The second controller monitors the shared memory; upon detecting the termination instruction, it ceases sending the periodic "wait" instruction to the control target. This prevents the second controller from continuously polling after a system restart.
4. A non-transitory computer readable medium storing a program causing a computer to execute a process for information processing, the computer including a first controller circuit that is controlled by a first operating system and a second controller circuit that is controlled by a second operating system different from the first operating system, the process comprising: outputting, using the first controller circuit, a waiting instruction waiting persistently until a response is transmitted from a control target; and converting, using the second controller circuit, the waiting instruction outputted from the first controller circuit into a periodic instruction waiting periodically until a response is transmitted from the control target, and outputting the periodic instruction to the control target.
A computer-readable storage medium contains instructions that, when executed, cause a computer to perform information processing using two controllers. The first controller, governed by a first operating system, outputs a persistent "wait" instruction, halting until a response is received from a control target. The second controller, under a different operating system, converts the persistent wait instruction into a periodic "wait" instruction. The second controller then outputs this periodic wait instruction to the control target, allowing the first controller to continue operation instead of being indefinitely blocked.
5. A non-transitory computer readable medium storing a program causing a computer to execute a process for information processing, the computer including a first controller circuit and a second controller circuit, the process comprising: converting, using the second controller circuit, a waiting instruction into a periodic instruction and outputting the periodic instruction to a control target, the waiting instruction being output from the first controller circuit and persistently waiting until a response is transmitted from the control target, the periodic instruction waiting periodically until a response is transmitted from the control target.
A computer-readable storage medium contains instructions that, when executed, cause a computer to perform information processing using two controllers. The second controller converts a persistent "wait" instruction from the first controller into a periodic "wait" instruction, sending the periodic instruction to a control target. The first controller's wait instruction is designed to halt until a response is received. The second controller transforms this into an instruction that waits periodically for a response, thus allowing the first controller to continue operating instead of being blocked indefinitely.
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September 5, 2017
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