Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A peripheral integrated circuit, IC, device for providing support to a data processing IC device, the peripheral IC device comprising: a fault detection component arranged to detect an occurrence of a fault condition within the data processing IC device; and a safe state control component arranged to, in response to detection of the fault condition occurring within the data processing IC device by the fault detection component: cause an input/output, I/O, cell of the data processing IC device to be configured into a scan-chain; and cause a predefined control signal to be scanned into the scan-chain to configure the I/O cell into a state corresponding to the predefined control signal.
A system uses a secondary IC to protect a main IC. This secondary IC has a fault detector that identifies problems (like crashes) in the main IC. If a fault is detected, a safe state controller in the secondary IC takes over. The safe state controller configures an I/O pin on the main IC into a scan chain (a series of registers). Then, the controller sends a predefined signal into this scan chain, forcing the I/O pin into a safe, predetermined state. This prevents the faulty main IC from causing further damage or unexpected behavior.
2. The peripheral IC device of claim 1 , wherein the peripheral IC device is arranged to be operably coupled to the data processing IC device via a serial peripheral interface, and the safe state control component is arranged to transmit command signals to the data processing IC device to cause the I/O cell of the data processing IC device to be configured into the scan-chain and to cause the predefined control signal to be scanned into the scan-chain via the serial peripheral interface.
This system uses a secondary IC communicating with a main IC via a Serial Peripheral Interface (SPI). When the secondary IC's fault detector identifies a fault in the main IC, its safe state controller sends commands via SPI. These commands tell the main IC to configure one of its I/O pins into a scan chain and then to scan in a pre-defined control signal, effectively forcing the I/O pin to a safe state. Communication between the two ICs to trigger the safety mechanism happens through the SPI.
3. The peripheral IC device of claim 1 , wherein the safe state control component is arranged to cause the I/O cell of the data processing IC device to be configured into the scan-chain by sending a command signal to a debug component of the data processing IC device instructing the debug component to configure the I/O cell of the data processing IC device into the scan-chain.
The secondary IC detects faults in a main IC and puts the main IC's I/O pins into a safe state. It does this by sending a command to the main IC's debug component. This command instructs the debug component to configure a specific I/O pin on the main IC into a scan chain, so that it can be controlled externally. The secondary IC indirectly manipulates the I/O pins via the main IC's debugging infrastructure.
4. The peripheral IC device of claim 3 , wherein the safe state control component is arranged to cause the predefined control signal to be scanned into the scan-chain by sending the command signal to the debug component of the data processing IC device comprising a control signal pattern to cause the debug component to scan in a control signal into the scan-chain to configure the I/O cell to comprise a logical level corresponding to the control signal pattern.
Building on the previous method, the secondary IC sends a command to the main IC's debug component when a fault is detected. This command includes a specific control signal pattern. The debug component then scans this pattern into the scan chain of a particular I/O pin. This forces the I/O pin to a defined logic level (high or low) corresponding to the control signal pattern sent by the secondary IC, placing the pin in a safe state.
5. The peripheral IC device of claim 3 , wherein the safe state control component is arranged to cause the predefined control signal to be scanned into the scan-chain by sending a command signal to the debug component of the data processing IC device to cause the debug component to scan in a control signal into the scan-chain to configure the I/O cell to comprise a high input impedance.
Building on the method using a debug component, the secondary IC sends a command to the main IC's debug component telling it to set an I/O pin to a high input impedance state when a fault occurs. The debug component configures the I/O pin into a scan chain and scans in a control signal that configures the I/O pin into this high-impedance state, which effectively disconnects the I/O pin and prevents it from causing unintended effects.
6. The peripheral IC device of claim 3 , wherein the safe state control component is arranged to cause the predefined control signal to be scanned into the scan-chain by sending a command signal to the debug component of the data processing IC device to cause the debug component to scan in a control signal into the scan-chain to configure the I/O cell to comprise a logical level corresponding to a predefined control signal pattern.
Building on the approach using the main IC's debug component, the secondary IC sends a command to the debug component, instructing it to apply a predefined control signal pattern to the scan chain of a particular I/O pin. This ensures the I/O pin is set to a specific, predetermined logic level (high or low) based on that control signal pattern, placing the pin in a safe and known state.
7. The peripheral IC device of claim 3 , wherein the safe state control component is operably coupled to a memory element and arranged to read therefrom a series of command signals for causing the I/O cell of the data processing IC device to be configured into the scan-chain and for causing a predefined control signal to be scanned into the scan-chain to configure the I/O cell into to a state corresponding to the predefined control signal.
The secondary IC uses a memory element (like a flash chip) to store a sequence of commands. When a fault is detected in the main IC, the secondary IC reads these commands from memory. The commands tell the main IC's debug component to configure an I/O pin into a scan chain and then scan in a specific control signal. This forces the I/O pin into a safe state corresponding to the scanned signal, ensuring a controlled response to the fault.
8. The peripheral IC device of claim 7 , wherein the safe state control component is further arranged to read from the memory element the control signal to be scanned into the scan-chain.
Expanding on the previous memory-based approach, the secondary IC not only reads the commands to configure the I/O pin into a scan chain from memory, but it also reads the specific control signal that needs to be scanned into that scan chain. This means the entire process, including the safe state value, is stored in and retrieved from memory, providing flexibility and configurability in responding to different fault conditions.
9. The peripheral IC device of claim 3 , wherein the safe state control component is operably coupled to a fuse element configurable to define the control signal to be scanned into the scan-chain.
The secondary IC uses a fuse element (programmable read-only memory) to define the control signal that will be scanned into the I/O pin's scan chain. When a fault is detected, the secondary IC reads the value from the fuse element and uses that value as the control signal to drive the I/O pin to a safe state. This provides a permanent, configurable way to set the safe state of the I/O pin.
10. The peripheral IC device of claim 3 , wherein the control signal to be scanned into the scan-chain is hardcoded into the peripheral IC device.
Instead of reading the control signal from memory or a fuse, the secondary IC has the control signal directly built into its design (hardcoded). When a fault is detected, the secondary IC uses this pre-defined, hardcoded signal to configure the main IC's I/O pin into a scan chain and then drive it to a safe state. This approach is simple and reliable, but less flexible than using memory or fuses.
11. The peripheral IC device of claim 1 , wherein the predefined control signal to be scanned into the scan-chain is arranged to force the I/O cell into to a state comprising at least one of: a high logical level; a low logical level; and a high input impedance level.
The pre-defined control signal scanned into the main IC's I/O pin is designed to force the I/O pin into one of the following safe states: a high logic level, a low logic level, or a high input impedance state (disconnected). The system chooses the most appropriate safe state based on the specific application and the potential risks associated with the fault condition.
12. The peripheral IC device of claim 1 , wherein the fault detection component is arranged to detect the occurrence of at least one of: an over-current condition within the data processing IC device; an over-voltage condition within the data processing IC device; an over-temperature condition within the data processing IC device; and a watchdog function not being serviced.
The fault detection component in the secondary IC can detect several types of fault conditions in the main IC, including: an over-current situation (too much current being drawn), an over-voltage situation (voltage too high), an over-temperature situation (IC overheating), or a watchdog timer failure (the main IC is not responding). The system uses these various detection methods to identify faults and trigger the safe state mechanism.
13. The peripheral IC device of claim 1 , wherein the fault detection component is arranged to detect the occurrence of fault conditions based on a notification received from the data processing IC device of the detection of a fault condition thereby.
The fault detection component in the secondary IC relies on the main IC to report fault conditions. If the main IC detects a fault internally, it sends a notification signal to the secondary IC. Upon receiving this notification, the secondary IC triggers the process of configuring the I/O pin into a scan chain and driving it to a safe state. This approach offloads fault detection to the main IC.
14. The peripheral IC device of claim 1 , wherein the support provided by the peripheral IC device to the data processing IC device comprises at least one from a group comprising: power regulator functionality; over current detection functionality; watchdog functionality; and physical layer communication functionality.
The secondary IC provides various types of support to the main IC, including: power regulation (ensuring stable power supply), over-current detection (preventing damage from excessive current draw), watchdog functionality (monitoring the main IC's responsiveness), and physical layer communication (handling the low-level details of communication). The safe state mechanism is integrated with these other support functions to protect the main IC.
15. A data processing integrated circuit, IC, device comprising a safety level configuration component, the safety level configuration component being controllable by a peripheral IC device operably coupled to the data processing IC device to: configure an input/output, I/O, cell of the data processing IC device to be configured into a scan-chain in response to a detection of a fault condition occurring within the data processing IC device; and cause a predefined control signal to be scanned into the scan-chain to configure the I/O cell into to a state corresponding to the predefined control signal.
A data processing IC has a safety level configuration component. This component can be controlled by a secondary IC connected to it. Upon detecting a fault, the secondary IC instructs the safety level configuration component in the main IC to configure an I/O pin into a scan chain. Then, a pre-defined control signal is scanned into this chain, forcing the I/O pin into a known, safe state. Thus, the main IC itself contains the logic for entering a safe state, triggered by an external fault detection signal.
16. The data processing IC device of claim 15 , wherein the I/O cell is arranged to be isolated from core functional components of the data processing IC device when configured into the scan-chain by the safety level configuration component.
When the main IC's safety level configuration component configures an I/O pin into a scan chain, the I/O pin is isolated from the main functional parts (core) of the main IC. This means that the safe state mechanism effectively disconnects the potentially faulty I/O pin from the rest of the IC, preventing it from interfering with or damaging other components.
17. The data processing IC device of claim 15 , wherein the safety level configuration component comprises a debug component of the data processing IC device.
The safety level configuration component in the main IC, responsible for configuring the I/O pin into a scan chain and applying the pre-defined control signal, is implemented using the debug component of the main IC. This reuses existing debugging infrastructure to provide the safety functionality, reducing the need for dedicated safety circuitry.
18. The data processing IC device of claim 15 , wherein the scan-chain comprises at least one boundary scan scan-chain.
The scan chain used to control the I/O pin is a boundary scan chain, a standard feature used for testing and debugging ICs. By using a boundary scan chain, the system leverages existing testing infrastructure to implement the safe state mechanism, providing a standardized and well-understood way to control the I/O pin.
19. The data processing IC device of claim 15 , wherein the data processing IC device comprises a microprocessor.
The data processing IC that utilizes the safe state mechanism is a microprocessor. This indicates the target application is likely a complex system requiring careful management of potential faults.
20. A method comprising: detecting, at a detection component, an occurrence of a fault condition within a data processing integrated circuit, IC, device; and in response to detection of the fault condition occurring within the data processing IC device: causing, by a safe state control component, an input/output, I/O, cell of the data processing IC device to be configured into a scan-chain; and causing, by the safe state control component, a predefined control signal to be scanned into the scan-chain to configure the I/O cell into a state corresponding to the predefined control signal.
A method involves detecting a fault condition within a data processing IC using a detection component. In response to detecting the fault, a safe state control component configures an I/O cell of the data processing IC into a scan-chain. Finally, the safe state control component causes a predefined control signal to be scanned into the scan-chain, configuring the I/O cell into a state corresponding to the predefined control signal.
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October 10, 2017
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