Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged; and an error correcting code (ECC) circuit configured to, generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors using the parity data in the read codeword on a per symbol basis based on the syndromes, the main data including first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row, the first data and the second data being assigned to one symbol of a plurality of symbols, the first memory cell and the second memory cell being adjacent to each other in the memory cell array.
A semiconductor memory device contains a memory cell array and an error correcting code (ECC) circuit. The ECC circuit generates parity data from main data, writes a codeword (main data + parity data) into the memory array, reads the codeword from a selected row to generate syndromes, and corrects errors in the codeword using the parity data on a "per symbol" basis. The main data consists of first data from a first memory cell and second data from a second memory cell in the same row. These first and second data values are treated as one "symbol", and the first and second memory cells are physically adjacent in the array.
2. The semiconductor memory device of claim 1 , wherein the main data includes 2 p bits and the parity data includes q bits, where q is greater than p and p and q are natural numbers equal to or greater than two, and wherein the ECC circuit is configured to generate q-bit check bits based on data in the read codeword, and generate the syndromes with q-bits based on the q-bit check bits and q-bit parity data in the read codeword.
In the semiconductor memory device described previously, the main data has '2p' bits and the parity data has 'q' bits, where 'q' is greater than 'p', and both 'p' and 'q' are natural numbers greater than or equal to two. The ECC circuit generates 'q'-bit check bits based on the read codeword and then calculates 'q'-bit syndromes using the 'q'-bit check bits and the 'q'-bit parity data from the read codeword. This means more parity bits are used than the amount of data represented by the symbol.
3. The semiconductor memory device of claim 2 , wherein the ECC circuit is configured to correct the errors if the one symbol includes errors equal to or smaller than two.
In the semiconductor memory device using an ECC circuit that generates 'q'-bit check bits based on the read codeword and then calculates 'q'-bit syndromes using the 'q'-bit check bits and the 'q'-bit parity data from the read codeword where the main data has '2p' bits and the parity data has 'q' bits, where 'q' is greater than 'p', and both 'p' and 'q' are natural numbers greater than or equal to two, the ECC circuit can correct errors if a symbol has one or two errors within it.
4. The semiconductor memory device of claim 2 , wherein values of the q-bit syndromes are linearly independent in first through third cases, and wherein the first case corresponds to a case when the first data has an error and the second data has no error, the second case corresponds to a case when the first data has no error and the second data has an error, and the third case corresponds to a case when the first data has an error and the second data has an error.
In the semiconductor memory device using an ECC circuit that generates 'q'-bit check bits based on the read codeword and then calculates 'q'-bit syndromes using the 'q'-bit check bits and the 'q'-bit parity data from the read codeword where the main data has '2p' bits and the parity data has 'q' bits, where 'q' is greater than 'p', and both 'p' and 'q' are natural numbers greater than or equal to two, the values of the 'q'-bit syndromes are linearly independent under three specific error scenarios: (1) when the first data has an error, but the second data does not; (2) when the first data has no error, but the second data does; and (3) when both the first and second data have errors. This ensures the ECC can distinguish between the different error types.
5. The semiconductor memory device of claim 2 , wherein the ECC circuit comprises: an encoder configured to generate the parity data based on the main data; and a decoder configured to generate the syndromes based on the read codeword to correct the errors.
In the semiconductor memory device described previously, the ECC circuit includes an encoder and a decoder. The encoder generates the parity data based on the main data before writing to memory. The decoder generates the syndromes based on the read codeword to correct errors that may have occurred during storage or retrieval.
6. The semiconductor memory device of claim 5 , wherein the encoder comprises a plurality of parity generators, each of the plurality of parity generators being configured to generate a corresponding parity bit of the q-bit parity data based on the 2 p -bit main data.
In the semiconductor memory device where the ECC circuit includes an encoder and a decoder, the encoder has multiple parity generators. Each parity generator creates one bit of the 'q'-bit parity data from the '2p'-bit main data. Each parity bit is generated independently based on the main data.
7. The semiconductor memory device of claim 5 , wherein the decoder comprises: a check bit generator configured to generate the q-bit check bits based on the main data of the read codeword; a syndrome generator configured to generate the q-bit syndromes based on the q-bit check bits and the parity data of the read codeword; and a corrector configured to correct the errors in the read codeword based on the q-bit syndromes.
In the semiconductor memory device where the ECC circuit includes an encoder and a decoder, the decoder consists of a check bit generator, a syndrome generator, and a corrector. The check bit generator produces 'q'-bit check bits based on the main data portion of the read codeword. The syndrome generator creates 'q'-bit syndromes using the 'q'-bit check bits and the parity data portion of the read codeword. Finally, the corrector fixes any errors in the read codeword based on these 'q'-bit syndromes.
8. The semiconductor memory device of claim 7 , wherein the syndrome generator is configured to generate the syndromes such that each syndrome has a logic level according to whether corresponding bits of the q-bit check bits and the q-bit parity data are equal to each other.
In the semiconductor memory device where the decoder consists of a check bit generator, a syndrome generator, and a corrector, the syndrome generator calculates syndromes where each syndrome bit's logic level indicates whether the corresponding bits of the 'q'-bit check bits and 'q'-bit parity data are equal. This effectively compares the calculated check bits with the stored parity data to identify discrepancies.
9. The semiconductor memory device of claim 8 , wherein the syndrome generator includes a plurality of logic elements, each of the plurality of logic elements being configured to perform an XOR operation on corresponding bits of the q-bit check bits and the q-bit parity data to generate a corresponding syndrome.
In the semiconductor memory device where the syndrome generator calculates syndromes where each syndrome bit's logic level indicates whether the corresponding bits of the 'q'-bit check bits and 'q'-bit parity data are equal, the syndrome generator employs multiple logic elements. Each logic element performs an XOR (exclusive OR) operation on corresponding bits from the 'q'-bit check bits and 'q'-bit parity data. The output of each XOR gate becomes a single syndrome bit.
10. The semiconductor memory device of claim 7 , wherein the corrector includes a plurality of unit correctors, and each of the plurality of unit correctors are configured to correct errors in each of the plurality of symbols on the per symbol basis if a number of the errors is equal to or smaller than two based on the syndromes.
In the semiconductor memory device where the decoder consists of a check bit generator, a syndrome generator, and a corrector, the corrector contains multiple unit correctors. Each unit corrector is responsible for correcting errors in a single "symbol" (made of the first and second data). It fixes the symbol if the number of errors within that symbol is one or two, based on the syndrome values.
11. The semiconductor memory device of claim 10 , wherein each of the unit correctors includes: a symbol decoder configured to determine whether at least one of the first data and the second data has an error based on the syndromes to generate first through third output signals; and a data corrector configured to correct errors in one of the plurality of symbols based on the first through third output signals.
This invention relates to semiconductor memory devices, specifically focusing on error correction in memory systems. The problem addressed is the need for efficient and reliable error detection and correction in memory data, particularly when dealing with multiple data streams or symbols. The semiconductor memory device includes a plurality of unit correctors, each responsible for processing data from memory cells. Each unit corrector contains a symbol decoder and a data corrector. The symbol decoder evaluates first and second data streams to determine if errors are present, using syndromes generated during error detection. The decoder produces three output signals based on this evaluation. The data corrector then uses these output signals to identify and correct errors in the symbols of the data. This process ensures data integrity by detecting and correcting errors at the symbol level, improving the reliability of the memory device. The invention is particularly useful in memory systems where data is stored in multiple symbols or where multiple data streams are processed simultaneously. By integrating error detection and correction at the unit corrector level, the device enhances fault tolerance and performance. The use of syndromes for error evaluation and subsequent correction provides a structured and efficient approach to maintaining data accuracy.
12. The semiconductor memory device of claim 11 , wherein the symbol decoder includes: a first sub decoder configured to provide the first output signal indicating whether the first data has an error based on the syndromes; a second sub decoder configured to provide the second output signal indicating whether the second data has an error based on the syndromes; and a third sub decoder configured to provide the third output signal indicating whether each of the first data and second data has an error based on the syndromes.
In the semiconductor memory device where each unit corrector has a symbol decoder and a data corrector, the symbol decoder contains three sub-decoders: a first sub-decoder, a second sub-decoder, and a third sub-decoder. The first sub-decoder creates a first output signal, indicating whether the first data has an error. The second sub-decoder creates a second output signal, indicating whether the second data has an error. The third sub-decoder provides a third output signal to indicate if both the first and second data have errors.
13. The semiconductor memory device of claim 11 , wherein the data corrector includes: a first logic element configured to perform an OR operation on the first output signal and the second output signal; a second logic element configured to perform an OR operation on the second output signal and the third output signal; a third logic element configured to perform an XOR operation on the first data and an output of the first logic element to output a first corrected data; and a fourth logic element configured to perform an XOR operation on the second data and an output of the second logic element to output a second corrected data.
In the semiconductor memory device where each unit corrector has a symbol decoder and a data corrector, the data corrector includes four logic elements. The first performs an OR operation on the first and second sub-decoder outputs from the symbol decoder. The second performs an OR operation on the second and third sub-decoder outputs from the symbol decoder. The third performs an XOR operation between the first data and the first logic element's output to produce the first corrected data. The fourth performs an XOR operation between the second data and the second logic element's output to produce the second corrected data.
14. The semiconductor memory device of claim 11 , wherein the data corrector is configured to invert the first data if the first data has an error, invert the second data if the second data has an error, and invert the first data and the second data if each of the first data and the second data has an error.
In the semiconductor memory device where each unit corrector has a symbol decoder and a data corrector, the data corrector operates by inverting the first data if the symbol decoder indicates the first data has an error, inverting the second data if the second data has an error, and inverting both the first and second data if the symbol decoder indicates both have errors. This directly flips the bits identified as being in error.
15. The semiconductor memory device of claim 1 , wherein each of the plurality of memory cells is a resistive type memory cell, and wherein the memory cell array includes a three-dimensional memory array in which at least one of word-lines and bit-lines are shared between levels.
In the semiconductor memory device including a memory cell array in which a plurality of memory cells are arranged; and an error correcting code (ECC) circuit configured to, generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors using the parity data in the read codeword on a per symbol basis based on the syndromes, the main data including first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row, the first data and the second data being assigned to one symbol of a plurality of symbols, the first memory cell and the second memory cell being adjacent to each other in the memory cell array, each of the memory cells is a resistive memory cell (e.g., ReRAM). The memory array is a 3D array where word lines or bit lines (or both) are shared across multiple levels/layers.
16. The semiconductor memory device of claim 1 , wherein first data of the first memory cell of the selected memory cell row and second data of the second memory cell of the selected memory cell row are assigned to a same symbol of the plurality of symbols.
In the semiconductor memory device including a memory cell array in which a plurality of memory cells are arranged; and an error correcting code (ECC) circuit configured to, generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors using the parity data in the read codeword on a per symbol basis based on the syndromes, the main data including first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row, the first data and the second data being assigned to one symbol of a plurality of symbols, the first memory cell and the second memory cell being adjacent to each other in the memory cell array, the first data from the first memory cell and the second data from the second memory cell are assigned to the *same* symbol.
17. The semiconductor memory device of claim 16 , wherein the first memory cell and the second memory cell are on a same word-line.
In the semiconductor memory device where the first data from the first memory cell and the second data from the second memory cell are assigned to the same symbol, the first memory cell and the second memory cell are located on the same word line within the memory array.
18. A device, comprising: a decoder configured to, receive a codeword from a selected memory cell row of a memory cell array, the received codeword including main data and parity data, the main data including first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row, the first memory cell and the second memory cell being adjacent to each other in the memory cell array, the first data and the second data being assigned to a first symbol of a plurality of symbols, generate an error indicator for the first symbol based on the received codeword, detect errors in the received codeword based on the error indicator, and correct the detected errors in the received codeword using the parity data.
A device includes a decoder. The decoder receives a codeword from a selected row in a memory array, which includes main data and parity data. The main data contains first data from a first memory cell and second data from a second, adjacent memory cell in the same row. These first and second data values are treated as a single symbol. The decoder generates an error indicator for the symbol based on the codeword, detects errors in the codeword based on the error indicator, and corrects these errors using the parity data.
19. The device of claim 18 , wherein the decoder is configured to generate the error indicator based on the parity data and check bit data derived from the main data.
In the device with a decoder that receives a codeword from a selected row in a memory array, which includes main data and parity data. The main data contains first data from a first memory cell and second data from a second, adjacent memory cell in the same row, where these first and second data values are treated as a single symbol, and generates an error indicator for the symbol based on the codeword, the decoder creates the error indicator using both the parity data and check bit data. The check bit data is derived from the main data within the received codeword.
20. The device of claim 18 , wherein the decoder is configured to generate the error indicator for the first symbol by, generating a first sub-error indicator for the first data, generating a second sub-error indicator for the second data, and combining the first sub-error indicator and the second error indicator.
In the device with a decoder that receives a codeword from a selected row in a memory array, which includes main data and parity data. The main data contains first data from a first memory cell and second data from a second, adjacent memory cell in the same row, where these first and second data values are treated as a single symbol, and generates an error indicator for the symbol based on the codeword, the decoder generates the error indicator for the symbol by first creating a sub-error indicator for the first data and a sub-error indicator for the second data, and then combines these two sub-error indicators.
21. The device of claim 20 , wherein the decoder is configured to detect errors in the first and second data based on the first error indicator, the second error indicator, and the third error indicator.
The invention relates to error detection in data processing systems, specifically for devices that handle multiple data streams with embedded error indicators. The problem addressed is ensuring reliable error detection across multiple data channels, particularly when data integrity is critical. The device includes a decoder that processes first and second data streams, each associated with respective error indicators. The decoder also receives a third error indicator, which may be derived from an external source or a separate error-checking mechanism. The decoder uses all three error indicators—first, second, and third—to detect errors in both the first and second data streams. This multi-indicator approach enhances error detection accuracy by cross-referencing multiple error signals, reducing false positives and improving system reliability. The device may be part of a larger system, such as a communication or storage system, where data integrity is paramount. The decoder's ability to leverage multiple error indicators ensures robust error detection, even in noisy or high-error-rate environments. This solution is particularly useful in applications where traditional single-indicator error detection methods are insufficient.
22. The device of 20 , wherein the combining includes performing an XOR operation on bits of the first error indicator and bits of the second error indicator.
In the device where the decoder generates the error indicator for the symbol by first creating a sub-error indicator for the first data and a sub-error indicator for the second data, and then combines these two sub-error indicators, the combination process involves performing an XOR (exclusive OR) operation on the bits of the first sub-error indicator and the bits of the second sub-error indicator.
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October 10, 2017
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