Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An apparatus comprising: a first receiver lane including a first decision feedback equalizer (DFE) to sample a first input signal based on first clock signals and generate a first data information and a first phase error information; a second receiver lane including a second DFE to sample a second input signal based on second clock signals and generate a second data information and a second phase error information; and a control unit to generate control information based on the first phase error information and the second phase error information, the first receiver lane to control phases of the first clock signals based on the control information, and the second receiver lane to control phases of the second clock signals based on the control information, wherein: the first receiver lane includes a first clock-data recovery loop to adjust the phases of the first clock signals based on the control information; and the second receiver lane includes a second clock-data recovery loop to adjust phases of the second clock signals based on the control information.
A wireline receiver apparatus uses two receiver lanes, each with a Decision Feedback Equalizer (DFE). The first DFE samples a first input signal using a first set of clock signals, generating data and phase error information. The second DFE does the same for a second input signal. A control unit combines phase error information from both lanes to generate control signals that adjust the phases of both sets of clock signals. Each receiver lane has a clock-data recovery loop to control timing based on the control information. This enables collaborative timing recovery across multiple lanes.
2. The apparatus of claim 1 , wherein: the first DFE includes first DFE slices, the first DFE slices including a number of first data comparators to provide the first data information, and a number of first phase error comparators to provide the first phase error information associated with the sampling of the first input signal, wherein the number of first phase error comparators is not greater than the number of first data comparators; and the second DFE includes second DFE slices, the second DFE slices including a number of second data comparators to provide the second data information, and a number of second phase error comparators to provide the second phase error information associated with the sampling of the second input signal, wherein the number of second phase error comparators is not greater than the number of second data comparators.
The wireline receiver apparatus described previously has DFEs composed of DFE slices. The first DFE contains slices with data comparators (for data information) and phase error comparators (for phase error information), with the number of phase error comparators being equal to or less than data comparators. The second DFE similarly contains slices with data and phase error comparators, with the number of phase error comparators being equal to or less than data comparators. By limiting the number of phase error comparators per slice, the complexity and power consumption of the DFE can be reduced.
3. The apparatus of claim 2 , wherein the number of first phase error comparators is less than the number of first data comparators, and the number of second phase error comparators is less than the number of second data comparators.
The wireline receiver apparatus featuring collaborative timing recovery where DFEs have slices with data and phase error comparators, has even fewer phase error comparators than data comparators in each DFE slice. Specifically, the number of phase error comparators is less than the number of data comparators in both the first and second DFEs. This further reduces the complexity of the phase error detection circuitry.
4. The apparatus of claim 2 , wherein each of the first DFE slices of the first DFE includes only one phase error comparator of the number of first phase error comparators, and each of the second DFE slices of the second DFE includes only one phase error comparator of the number of second phase error comparators.
The wireline receiver apparatus uses DFEs with slices that contain data and phase error comparators. Each DFE slice in both receiver lanes contains only a single phase error comparator. Therefore, the number of phase error comparators is one per slice. This simplification minimizes the hardware required for phase error detection within each DFE slice while still allowing for timing adjustments.
5. The apparatus of claim 1 , wherein each of the first DFE and the second DFE includes a speculative tap.
The wireline receiver apparatus featuring collaborative timing recovery between two receiver lanes includes a speculative tap in each of the DFEs. The speculative tap allows the DFE to predict and compensate for inter-symbol interference (ISI) beyond the normal reach of the DFE taps, which improves performance at high data rates.
6. An apparatus comprising: a first receiver lane including a first decision feedback equalizer (DFE) to sample a first input signal based on first clock signals and generate a first data information and a first phase error information; a second receiver lane including a second DFE to sample a second input signal based on second clock signals and generate a second data information and a second phase error information; and a control unit to generate control information based on the first phase error information and the second phase error information, the first receiver lane to control phases of the first clock signals based on the control information, and the second receiver lane to control phases of the second clock signals based on the control information, wherein: the first receiver lane is to provide a first additional control information based on the first phase error information, and to select one of the control information and the first additional control information to generate a first selected control information in order to control timing of the first clock signals based on the first selected control information; and the second receiver lane is to provide a second additional control information based on the second phase error information, and to select one of the control information and the second additional control information to generate a second selected control information in order to control timing of the second clock signals based on the second selected control information.
A wireline receiver apparatus comprises two receiver lanes, each with a DFE that samples an input signal based on clock signals, generating data and phase error information. A control unit generates control information based on the phase error information from both lanes. Each receiver lane also calculates its own additional control information based on its phase error. A selection mechanism chooses between the shared control information and the lane-specific additional control information to control the timing of the clock signals in each lane. This provides both collaborative and independent timing control.
7. The apparatus of claim 1 , further comprising: a third receiver lane including a third DFE to sample a third input signal based on third clock signals and generate a third data information and a third phase error information; and a fourth receiver lane including a fourth DFE to sample a fourth input signal based on fourth clock signals and generate a fourth data information and a fourth phase error information, the control unit to generate the control information based on the first phase error information, the second phase error information, the third phase error information, and the fourth phase error information, the third receiver lane to control phases of the third clock signals based on the control information, and the fourth receiver lane to control phases of the fourth clock signals based on the control information.
The wireline receiver apparatus utilizes four receiver lanes, each with a DFE to sample an input signal based on clock signals, generating data and phase error information. A central control unit generates control information based on the phase error information from all four lanes. This control information is then used to adjust the phases of the clock signals in all four receiver lanes, achieving collaborative timing recovery across a higher number of lanes.
8. The apparatus of claim 7 , wherein the first clock signals include quadrature clock signals, the second clock signals include quadrature clock signals, the third clock signals include quadrature clock signals, and the fourth clock signals include quadrature clock signals, and the quadrature clock signals of the first clock signals are the same as the quadrature clock signals of each of the second clock signals, the third clock signals, and the fourth clock signals.
In the four-lane wireline receiver apparatus with collaborative timing recovery, each lane uses quadrature clock signals for sampling. Importantly, the quadrature clock signals used by the first, second, third, and fourth receiver lanes are the same. This simplifies the clock distribution network and ensures that all lanes are synchronized to a common timing reference.
9. The apparatus of claim 1 , wherein apparatus comprises a circuit board including conductive lines, a first device on the circuit board and coupled to the conductive lines, and a second device on the circuit board and coupled to the conductive lines, wherein the first device includes the first receiver lane, the second receiver lane, and the control unit.
The wireline receiver apparatus featuring collaborative timing recovery is implemented on a circuit board. The board has conductive lines connecting a first and second device. The first device contains the receiver lanes (including the DFEs) and the control unit. This configuration integrates the receiver functionality into a single device that communicates with other components on the board through the conductive lines.
10. The apparatus of claim of claim 9 , wherein the conductive lines conform with at least one of Universal Serial Bus (USB), DisplayPort (DP), High-Definition Multimedia Interface (HDMI), Thunderbolt, and Peripheral Component Interconnect Express (PCIe) specifications.
The wireline receiver apparatus, implemented on a circuit board, uses conductive lines that conform to common high-speed communication standards. These standards include Universal Serial Bus (USB), DisplayPort (DP), High-Definition Multimedia Interface (HDMI), Thunderbolt, and Peripheral Component Interconnect Express (PCIe). This ensures compatibility with a wide range of devices and interfaces.
11. An apparatus comprising: an input to receive an input signal; additional inputs to receive clock signals having different phases to sample the input signal; and a decision feedback equalizer (DFE) including a first DFE slice coupled to the input node, and a second DFE slice coupled to the input node, the DFE including a number of data comparators and a number of phase error comparators, wherein: the first DFE slice includes a first summer including a first summer output node, first comparators of the number of data comparators and at least one phase error comparator of the number of phase error comparators, each comparator of the first comparators includes an input node coupled to the first summer output node, the at least one phase error comparator includes an input node coupled to the first summer output node, and the quantity of the least one first phase error comparator of the first DFE slice is not greater than a quantity of the first comparators; and the second DFE slice includes a second summer including a second summer output node, second comparators of the number of data comparators and at least one second phase error comparator of the number of phase error comparators, each comparator of the second comparators includes an input node coupled to the second summer output node, the at least one second phase error comparator includes an input node coupled to the second summer output node, and the quantity of the least one second phase error comparator is not greater than a quantity of the second comparators.
A wireline receiver apparatus has an input for a signal and inputs for multi-phase clock signals. A Decision Feedback Equalizer (DFE) contains multiple DFE slices. Each DFE slice contains a summer with an output node. Each slice also has data comparators and at least one phase error comparator. All comparators (data and phase error) in a given slice are connected to the summer output. Critically, the number of phase error comparators in each slice is equal to or less than the number of data comparators in that slice.
12. The apparatus of claim 11 , wherein the quantity of the least one first phase error comparator is one, and the quantity of the least one second phase error comparator is one.
The wireline receiver apparatus, featuring a DFE composed of slices with data comparators and at least one phase error comparator, has only one phase error comparator per DFE slice. Therefore, in the first and second DFE slices, the number of phase error comparators is one. This simplifies the phase error detection within each slice.
13. The apparatus of claim 11 , wherein the quantity of the least one first phase error comparator is less than the quantity of the first comparators, and the quantity of the least one second phase error comparator is less than the quantity of the second comparators.
The wireline receiver apparatus with DFEs composed of slices with data and phase error comparators has fewer phase error comparators than data comparators within each slice. Specifically, the number of phase error comparators in the first and second DFE slices is less than the number of data comparators in each of those slices. This further reduces hardware complexity.
14. The apparatus of claim 11 , wherein the quantity of the least one first phase error comparator is equal to one-half of the quantity of the first comparators, and the quantity of the least one second phase error comparator is equal to one-half of the quantity of the second comparators.
The wireline receiver apparatus with DFEs composed of slices with data and phase error comparators has a ratio of phase error to data comparators of 1:2. Specifically, the number of phase error comparators is equal to one-half of the number of data comparators in both the first and second DFE slices.
15. The apparatus of claim 11 , wherein the number of data comparators is to provide data information based on the sampling of the input signal, and the number of phase error comparators is to provide phase error information associated with the sampling of the input signal, and each phase error comparator of the number of phase error comparators is to provide a portion of the phase error information based on values of three consecutive bits of the data information.
The wireline receiver apparatus uses a DFE with data and phase error comparators. The data comparators provide data information by sampling the input signal. The phase error comparators provide phase error information. Each phase error comparator generates its portion of the phase error information using the values of three consecutive bits of the data information. This phase error detection uses the most recent data bits.
16. The apparatus of claim 11 , wherein the DFE includes multiple taps, the multiple taps including a speculative first tap.
The wireline receiver apparatus employs a DFE with multiple taps, including a speculative first tap. This speculative tap allows the DFE to predict and compensate for inter-symbol interference (ISI) beyond the normal reach of the DFE taps, which improves performance at high data rates by anticipating future signal distortions.
17. A method comprising: sampling a first input signal based on first clock signals to generate a first data information and a first phase error information, sampling being performed at a first decision feedback equalizer (DFE) of a first receiver lane; sampling a second input signal based on second clock signals to generate a second data information and a second phase error information, sampling being performed at a second DFE of a second receiver lane; generating control information based on the first phase error information and the second phase error information; controlling phases of the first clock signals based on the control information; and controlling phases of the second clock signals based on the control information, wherein the first phase error information is generated based on values of three consecutive bits of the first data information, and the second phase error information is generated based on values of three consecutive bits of the second data information, and the first phase error information is generated based on a first bit of the three consecutive bits of the first data information having a first value, a second bit of the three consecutive bits of the first data information having either the first value or a second value, and a third bit of the three consecutive bits of the first data information having the second value, and the first bit of the three consecutive bits of the first data information is sampled before the second and third bits of the three consecutive bits of the first data information are sampled; and the second phase error information is generated based on a first bit of the three consecutive bits of the second data information having the first value, a second bit of the three consecutive bits of the second data information having either the first value or the second value, and a third bit of the three consecutive bits of the second data information having the second value, and the first bit of the three consecutive bits of the second data information is sampled before the second and third bits of the three consecutive bits of the second data information are sampled.
A method performs collaborative timing recovery using two receiver lanes. A first DFE in the first lane samples a first input signal to generate data and phase error information. A second DFE in the second lane does the same. Control information is generated based on the phase error from both lanes. The phases of the clock signals in each lane are then controlled based on this shared control information. The phase error information is based on three consecutive bits of data. Specifically, the first bit has one value, the last bit has a different value, and the middle bit can have either value. The first bit is sampled before the other two bits.
Unknown
October 17, 2017
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.