Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A data processing apparatus for accessing a plurality of memories, wherein the data processing apparatus comprises: a function control circuitry, utilized to record a first memory address where a first function is implemented in the function control circuitry after the first function is implemented and to determine which one of the plurality of memories is a target memory according to the first memory address; and an address generation circuitry, utilized to output the first memory address to the target memory, wherein the function control circuitry is configured to determine the target memory in the same processing cycle in which the address generation circuitry is configured to output the first memory address.
A data processing apparatus accesses multiple memories. It includes a function control circuit that records the memory address where a function was just executed. Using this address, it determines which of the memories is the "target" memory. An address generation circuit then outputs the recorded memory address to that target memory. The function control circuit determines the target memory and the address generation circuit outputs the memory address in the same processing cycle, improving speed.
2. The data processing apparatus as claimed in claim 1 , wherein when a second function is implemented after the implementation of the first function, the function control circuitry records a second memory address where the second function is implemented in the function control circuitry after the second function is implemented and determines which one of the plurality of memories is the target memory according to the second memory address rather than the first memory address.
Building upon the data processing apparatus that accesses multiple memories, as described in claim 1, when a second function runs after the first, the function control circuit then records the memory address of this second function. The function control circuit determines the target memory based on this second address instead of the first address. This allows the system to track and switch target memories dynamically as different functions are executed sequentially.
3. The data processing apparatus as claimed in claim 1 , wherein the function control circuitry further indicates whether the target memory is valid, and the address generation circuitry outputs the first memory address to the target memory when the function control circuitry indicates the target memory is valid.
Building upon the data processing apparatus that accesses multiple memories, as described in claim 1, the function control circuit also indicates whether the determined target memory is actually a valid memory location. The address generation circuit only outputs the memory address to the target memory if the function control circuit confirms that the target memory is valid, preventing access to invalid memory locations.
4. The data processing apparatus as claimed in claim 3 , wherein the address generation circuitry outputs the first memory address to each one of the plurality of memories when the function control circuitry indicates the target memory is not valid.
Building upon the data processing apparatus described in claim 3, if the function control circuit indicates the target memory is NOT valid, the address generation circuit outputs the memory address to *all* of the memories, rather than just the invalid target memory. This can be used for broadcasting or searching across all memories when the target memory is unknown or unreliable.
5. The data processing apparatus as claimed in claim 1 , wherein before the address generation circuitry outputs the first memory address to the target memory, the function control circuitry further indicates whether the first function is going to be implemented, and the address generation circuitry outputs the first memory address to each one of the plurality of memories when the first function is going to be implemented.
Building upon the data processing apparatus that accesses multiple memories, as described in claim 1, before the address generation circuit outputs the memory address to the target memory, the function control circuit first indicates whether the function is even *going* to be executed. If the function is about to be implemented, the address generation circuit outputs the address to each of the multiple memories, rather than only the target.
6. The data processing apparatus as claimed in claim 5 , wherein the data processing apparatus further comprises a core circuitry, and the first function comprises a call operation and/or a return operation executed by the core circuitry.
Building upon the data processing apparatus described in claim 5, a core circuit executes functions which may include call operations or return operations. The function control circuit indicates whether these call/return functions are going to be executed. If so, the address generation circuitry outputs the memory address to each of the multiple memories. This handles function calls and returns that may require memory access across multiple locations.
7. The data processing apparatus as claimed in claim 1 , wherein the first function is stored at only one of the plurality of memories.
Building upon the data processing apparatus that accesses multiple memories, as described in claim 1, the function itself (the code or data being accessed) is stored in only *one* of the multiple memories. The system identifies *which* single memory the function resides in, allowing for targeted memory access.
8. The data processing apparatus as claimed in claim 1 , wherein before the function control circuitry records the first memory address where the first function is implemented, the address generation circuitry further executes to: output the first memory address to each one of the plurality of memories when there is no first memory address recorded on the function control circuitry.
Building upon the data processing apparatus that accesses multiple memories, as described in claim 1, *before* the function control circuit records any memory address, the address generation circuit initially outputs the memory address to *all* of the memories. This initial broadcast occurs only when there's no previously recorded memory address in the function control circuit, acting as a default or initialization step.
9. The data processing apparatus as claimed in claim 1 , wherein after the address generation circuitry outputs the first memory address to the target memory, the target memory outputs data regarding the first function to the data processing apparatus.
Building upon the data processing apparatus that accesses multiple memories, as described in claim 1, after the address generation circuit sends the memory address to the target memory, the target memory then sends back the data associated with that address (the "function data") to the data processing apparatus. This completes the read operation, retrieving the function's data.
10. A data processing method, utilized for a data processing apparatus to access a plurality of memories, comprising: recording a first memory address where a first function is implemented in a function control circuitry of the data processing apparatus after the first function is implemented; determining which one of the plurality of memories is a target memory according to the first memory address; and outputting the first memory address to the target memory, wherein the target memory is determined in the same processing cycle in which the first memory address is outputted.
A method for a data processing apparatus to access multiple memories involves: Recording the memory address where a function was just executed; determining which of the memories is the "target" memory based on that address; and outputting the recorded memory address to the determined target memory. This determining and outputting occurs in the same processing cycle for speed.
11. The data processing method as claimed in claim 10 , further comprising recording a second memory address where a second function is implemented in the function control circuitry after the second function is implemented, and determining which one of the plurality of memories is the target memory according to the second memory address rather than the first memory address, wherein the second function is implemented after the implementation of the first function.
Building upon the data processing method described in claim 10, a second function executed after the first causes a new memory address to be recorded. The target memory is then determined based on *this* second address, not the first. This allows the system to dynamically switch the target memory as different functions are executed sequentially.
12. The data processing method as claimed in claim 10 , further comprising indicating whether the target memory is valid, and outputting the first memory address to the target memory when the function control circuitry indicates the target memory is valid.
Building upon the data processing method described in claim 10, the method also includes indicating whether the target memory is valid. Outputting the memory address to the target memory happens *only* if the target memory is indicated as being valid. This avoids writing to invalid memory locations.
13. The data processing method as claimed in claim 12 , further comprising outputting the first memory address to each one of the plurality of memories when the function control circuitry indicates the target memory is not valid.
Building upon the data processing method described in claim 12, if the target memory is indicated as *not* valid, the memory address is output to *all* of the multiple memories, not just the invalid target memory. This enables broadcasting or searching across all memories.
14. The data processing method as claimed in claim 10 , wherein before outputting the first memory address to the target memory, the data processing method further comprises: indicating whether the first function is going to be implemented; and outputting the first memory address to each one of the plurality of memories when the first function is going to be implemented.
Building upon the data processing method described in claim 10, *before* outputting the memory address to the target memory, the method includes indicating whether the function is *going* to be executed. If so, the address is sent to *all* of the multiple memories. This allows for speculative access or pre-fetching.
15. The data processing method as claimed in claim 14 , wherein the first function comprises a call operation and/or a return operation.
Building upon the data processing method described in claim 14, the "function" being executed or about to be executed includes a call operation or a return operation. The determination of executing the call or return is a condition for sending the address to all memories.
16. The data processing method as claimed in claim 10 , further comprising storing the first function in only one of the plurality of memories.
Building upon the data processing method described in claim 10, the function itself is stored in only *one* of the multiple memories. The method focuses on efficiently identifying and accessing this single memory location.
17. The data processing method as claimed in claim 10 , wherein before recording the first memory address in the function control circuitry, the data processing method further comprises: outputting the first memory address to each one of the plurality of memories when there is no first memory address recorded on the function control circuitry.
Building upon the data processing method described in claim 10, *before* recording any memory address, the method initially outputs the memory address to *all* of the memories. This occurs only when there is no previously recorded memory address, acting as an initialization step.
18. The data processing method as claimed in claim 10 , further comprising after outputting the first memory address to the target memory, outputting data regarding the first function to the data processing apparatus.
Building upon the data processing method described in claim 10, *after* the memory address is output to the target memory, the target memory outputs the data associated with that memory address back to the data processing apparatus.
19. A data processing apparatus for accessing a plurality of memories, wherein the data processing apparatus comprises: a core circuitry, utilized to output a fetch memory address; a function control circuitry, utilized to receive the fetch memory address and determine one of the plurality of memories as a target memory which the fetch memory address is located by recording the target memory when it is accessed; and an address generation circuitry, utilized to output the fetch memory address to the target memory.
A data processing apparatus accessing multiple memories consists of a core circuit that outputs a fetch memory address. A function control circuit receives this address and determines the target memory by recording the target memory when it is accessed. An address generation circuit then outputs the fetch memory address to this determined target memory.
20. A data processing apparatus for accessing a plurality of memories, wherein the data processing apparatus comprises: an address generation circuitry, utilized to output a fetch memory address to a target memory; and a function control circuitry, utilized to determine one of the plurality of memories as the target memory corresponding to data to be accessed by recording which one of the plurality of memories is recently accessed and assigning the recently accessed memory as the target memory.
A data processing apparatus for accessing multiple memories includes an address generation circuit that outputs a fetch memory address to a target memory. A function control circuit determines which of the multiple memories should be the target by recording which memory was recently accessed, and then assigning that recently accessed memory as the target memory. This allows for faster access due to locality of reference.
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October 31, 2017
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