9817776

Memory Descriptor List Caching and Pipeline Processing

PublishedNovember 14, 2017
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Technical Abstract

Patent Claims
20 claims

Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.

Claim 1

Original Legal Text

1. A method for accessing data within a buffer, the method comprising: receiving a handle by at least one stage of a processing pipeline of a computing device, wherein the at least one stage is to access the data within the buffer and is to perform at least some processing on the data; requesting, by the at least one stage, a memory descriptor list that corresponds to the received handle, wherein the memory descriptor list is cached in a buffer information cache and describes at least a location of the buffer; in response to the request, receiving the memory descriptor list; accessing, by the at least one stage, the data using information from the received memory descriptor list; and processing the data by the at least one stage.

Plain English Translation

A method for a processing pipeline to access data in a buffer: A stage in the pipeline receives a "handle" (an identifier). This stage needs to process data within the buffer. It requests the memory descriptor list (MDL) that corresponds to the handle. The MDL, which describes the buffer's location, is retrieved from a cache. The stage then uses the information in the MDL to locate and access the data in the buffer, and finally processes the data. This allows stages in a processing pipeline to efficiently access data in a buffer using a handle and a cached memory descriptor list.

Claim 2

Original Legal Text

2. The method of claim 1 , further comprising: creating the buffer via a probe, lock, and map operation, wherein the accessing and processing of the data is performed without using the probe, lock, and map operation.

Plain English Translation

The method for a processing pipeline to access data in a buffer (where a stage in the pipeline receives a handle, requests the corresponding memory descriptor list (MDL) from a cache, receives the MDL, accesses the data using information from the MDL, and processes the data) is improved by creating the buffer using a "probe, lock, and map" operation, but the subsequent access and processing of the data are performed *without* needing to repeat that "probe, lock, and map" operation. This avoids the overhead of these operations for each access, improving efficiency.

Claim 3

Original Legal Text

3. The method of claim 1 , wherein the memory descriptor list is cached in a buffer information cache of a device driver, and wherein the device driver is executing in a kernel mode of an operating system of the computing device.

Plain English Translation

The method for a processing pipeline to access data in a buffer (where a stage in the pipeline receives a handle, requests the corresponding memory descriptor list (MDL) from a cache, receives the MDL, accesses the data using information from the MDL, and processes the data) has the memory descriptor list cached within a buffer information cache that's part of a device driver. This device driver runs in the kernel mode of the operating system. This places the caching functionality within the protected kernel space for better security and system-level access.

Claim 4

Original Legal Text

4. The method of claim 3 , wherein the device driver is for a camera, and wherein the data represents an image.

Plain English Translation

The method for a processing pipeline to access data in a buffer (where a stage in the pipeline receives a handle, requests the corresponding memory descriptor list (MDL) from a cache managed by a device driver running in kernel mode, receives the MDL, accesses the data using information from the MDL, and processes the data) is applied to a camera device driver. In this specific case, the data in the buffer represents an image. The pipeline stages process image data efficiently through the handle and cached memory descriptor list mechanism.

Claim 5

Original Legal Text

5. The method of claim 1 , wherein the at least one stage is executing in a user mode of an operating system of the computing device.

Plain English Translation

The method for a processing pipeline to access data in a buffer (where a stage in the pipeline receives a handle, requests the corresponding memory descriptor list (MDL) from a cache, receives the MDL, accesses the data using information from the MDL, and processes the data) is used where the stage that accesses the data runs in user mode of the operating system. This enables applications to access and process the buffer data through the memory descriptor list caching mechanism, without requiring kernel-level privileges for each access.

Claim 6

Original Legal Text

6. The method of claim 1 , wherein the buffer is part of a circular allocator.

Plain English Translation

The method for a processing pipeline to access data in a buffer (where a stage in the pipeline receives a handle, requests the corresponding memory descriptor list (MDL) from a cache, receives the MDL, accesses the data using information from the MDL, and processes the data) is adapted for buffers that are part of a circular allocator. Using a circular allocator allows reuse of buffer space, and this method enables efficient access to those reused buffer sections through the handle and cached MDL.

Claim 7

Original Legal Text

7. The method of claim 6 , wherein the circular allocator is executing in a user mode of an operating system of the computing device.

Plain English Translation

The method for a processing pipeline to access data in a buffer that is part of a circular allocator (where a stage in the pipeline receives a handle, requests the corresponding memory descriptor list (MDL) from a cache, receives the MDL, accesses the data using information from the MDL, and processes the data) is used when the circular allocator is operating in user mode of the operating system. This allows user applications to manage and access circular buffers efficiently with the memory descriptor list caching system.

Claim 8

Original Legal Text

8. A computing device for pipeline processing of data, the computing device comprising: a processing system configured to perform one or more operations; and memory configured to maintain instructions that are executable by the processing system to: create a buffer in the memory by performing a probe, lock, and map operation; cache, in a buffer information cache, a memory descriptor list that describes at least a location of the buffer along with a handle corresponding to the memory descriptor list; receive the handle by at least one stage of a pipeline that is to access data within the buffer; request, by the at least one stage using the received handle, the memory descriptor list; receive, by the at least one stage, the memory descriptor list; and access, by the at least one stage, the data within the buffer using the received memory descriptor list.

Plain English Translation

A computing device designed for pipeline processing of data: It has a processing system and memory containing instructions to: 1) Create a buffer in memory using a "probe, lock, and map" operation. 2) Store (cache) a memory descriptor list (MDL) describing the buffer's location along with a handle in a buffer information cache. 3) A stage in the pipeline receives the handle. 4) The stage requests the MDL using the handle. 5) The stage receives the MDL. 6) The stage accesses the buffer's data using the received MDL. This device utilizes caching and handles for fast data access in pipelines.

Claim 9

Original Legal Text

9. The computing device of claim 8 , wherein the creation of the buffer and the caching of the memory descriptor list are performed by an operating system of the computing device.

Plain English Translation

The computing device for pipeline processing of data (with a processing system and memory configured to create a buffer with probe, lock, and map, cache an MDL with a handle, receive the handle by a pipeline stage, request and receive the MDL, and access data using the MDL) performs the initial buffer creation and memory descriptor list caching operations via the operating system. This delegates the memory management and caching functionality to the OS for better resource utilization and security.

Claim 10

Original Legal Text

10. The computing device of claim 8 , wherein the access of the data within the buffer is performed without using the probe, lock, and map operation.

Plain English Translation

In the computing device for pipeline processing of data (with a processing system and memory configured to create a buffer with probe, lock, and map, cache an MDL with a handle, receive the handle by a pipeline stage, request and receive the MDL, and access data using the MDL), the data access within the buffer happens *without* needing to repeat the "probe, lock, and map" operation. Once the buffer is created and the MDL is cached, subsequent accesses leverage the handle/MDL mechanism, reducing overhead.

Claim 11

Original Legal Text

11. The computing device of claim 8 , wherein the access to the data is performed by the one or more stages by using the handle as part of a call for the memory descriptor list for the buffer from the buffer information cache without repeating the probe, lock, and map operation.

Plain English Translation

In the computing device for pipeline processing of data (with a processing system and memory configured to create a buffer with probe, lock, and map, cache an MDL with a handle, receive the handle by a pipeline stage, request and receive the MDL, and access data using the MDL), the data access happens by the pipeline stages using the handle to call for the memory descriptor list from the buffer information cache, and this whole process happens *without* repeating the probe, lock, and map operation. This emphasizes the performance gain by avoiding repeated memory mapping operations.

Claim 12

Original Legal Text

12. The computing device of claim 8 , wherein the buffer information cache is maintained by device driver that is configured for execution in a kernel mode of an operating system of the computing device.

Plain English Translation

In the computing device for pipeline processing of data (with a processing system and memory configured to create a buffer with probe, lock, and map, cache an MDL with a handle, receive the handle by a pipeline stage, request and receive the MDL, and access data using the MDL), the buffer information cache is maintained by a device driver. This device driver is configured to execute in the kernel mode of the operating system. This ensures the cache is managed within a protected system environment.

Claim 13

Original Legal Text

13. The computing device of claim 12 , wherein the at least one stage is configured to execute in a user mode of the operating system of the computing device.

Plain English Translation

In the computing device for pipeline processing of data (with a processing system and memory configured to create a buffer with probe, lock, and map, cache an MDL with a handle in a device driver executing in kernel mode, receive the handle by a pipeline stage, request and receive the MDL, and access data using the MDL), the pipeline stage that accesses the data is configured to run in the user mode of the operating system. This allows user applications to leverage the cached MDL mechanism without direct kernel interaction.

Claim 14

Original Legal Text

14. The computing device of claim 12 , wherein the device driver is for a camera, and wherein the data represents an image.

Plain English Translation

In the computing device for pipeline processing of data (with a processing system and memory configured to create a buffer with probe, lock, and map, cache an MDL with a handle in a device driver executing in kernel mode, receive the handle by a pipeline stage, request and receive the MDL, and access data using the MDL), the device driver is for a camera, and the data represents an image. This specifies the application of the invention to image processing pipelines within camera systems.

Claim 15

Original Legal Text

15. A method for enabling data processing, the method comprising: creating a buffer in memory of a computing device; caching a memory descriptor list in a buffer information cache, wherein the memory descriptor list describes the buffer and has associated therewith a handle to the memory descriptor list; receiving a request for the memory descriptor list from a process that is to access data in the buffer, the request for the memory descriptor list including the handle; in response to the received request for the memory descriptor list, providing the memory descriptor list to the process; receiving a request to access the data in the buffer from the process, the request to access the data in the buffer including at least a portion of information from the memory descriptor list; and in response to the received request to access the data in the buffer, providing access to the data in the buffer to the process.

Plain English Translation

A method for enabling data processing involves these steps: Create a buffer in memory. Cache a memory descriptor list (MDL) in a buffer information cache. The MDL describes the buffer and is associated with a handle. Receive a request for the MDL (including the handle) from a process that needs to access data in the buffer. Provide the MDL to the process in response to the request. Receive a request from the process to access the data (including information from the MDL). Provide the process with access to the data in the buffer.

Claim 16

Original Legal Text

16. The method of claim 15 , wherein the buffer information cache is maintained by a device driver that is configured for execution in a kernel mode of an operating system of the computing device, and wherein the process is executing in a user mode of the operating system.

Plain English Translation

The method for enabling data processing (creating a buffer, caching an MDL with a handle, receiving and responding to MDL and data access requests from a process) has the buffer information cache maintained by a device driver executing in kernel mode. The process accessing the data runs in user mode. This separates memory management and data access privileges. The kernel-mode driver handles the cache, while user-mode processes can efficiently request and use the cached MDL for data access.

Claim 17

Original Legal Text

17. The method of claim 16 , wherein the device driver is for a camera and the data in the buffer is an image.

Plain English Translation

In the method for enabling data processing with kernel-mode driver and user-mode process (creating a buffer, caching an MDL with a handle in a device driver executing in kernel mode, receiving and responding to MDL and data access requests from a user-mode process), the device driver is for a camera, and the data in the buffer is an image. This specifically applies the method to camera systems where image data needs to be efficiently accessed and processed.

Claim 18

Original Legal Text

18. The method of claim 15 , further comprising: rendering image data within the buffer.

Plain English Translation

The method for enabling data processing (creating a buffer, caching an MDL with a handle, receiving and responding to MDL and data access requests from a process) further includes rendering image data within the buffer. This indicates the processed data is used for display or other visual presentation, implying this method is used in graphics or display systems.

Claim 19

Original Legal Text

19. The method of claim 15 , wherein the creating includes: using a probe, lock, and map operation, and wherein the access to the data is provided via the handle and the memory descriptor list without repeating the probe, lock, and map operation.

Plain English Translation

In the method for enabling data processing (creating a buffer, caching an MDL with a handle, receiving and responding to MDL and data access requests from a process), the buffer creation involves a "probe, lock, and map" operation. However, data access is provided via the handle and memory descriptor list *without* repeating the "probe, lock, and map" operation. This avoids the overhead of repeated memory mapping for efficient data access after initial setup.

Claim 20

Original Legal Text

20. The method of claim 15 , further comprising: detecting that an amount of available space in the memory has dropped below a threshold; and in response to the detecting, reverting to use of the probe, lock, and map operation instead of the buffer information cache.

Plain English Translation

The method for enabling data processing (creating a buffer, caching an MDL with a handle, receiving and responding to MDL and data access requests from a process) includes detecting when available memory drops below a certain threshold. If this happens, the system switches *back* to using the "probe, lock, and map" operation instead of relying on the buffer information cache. This provides a fallback mechanism when memory resources are constrained, potentially sacrificing some performance for stability.

Patent Metadata

Filing Date

Unknown

Publication Date

November 14, 2017

Inventors

Mei L. Wilson
Jitesh Krishnan
Sathyanarayanan Karivaradaswamy

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Memory Descriptor List Caching and Pipeline Processing