Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method for designing an integrated circuit device, comprising: using a computer system, providing a simulation model for a three-dimensional integrated circuit device implementing an integrated circuit design, the device having a first chip superposing a second chip, the first chip having a first substrate having opposite topside and backside surfaces and the second chip having opposite topside and backside surfaces, the first chip having an insulating layer on the backside surface of the first substrate, wherein first and second TSVs each extend entirely through the first substrate, wherein a conductive path electrically connects the first TSV on a first end to the first substrate topside surface, and on a second end to the first substrate backside surface, thereby suppressing latch-up in the first chip, the second end of the first TSV being electrically insulated from the second chip, and wherein the second TSV electrically connects through a via in the insulating layer on the backside surface of the first substrate to an electrically conductive feature on the topside surface of the second chip; and generating tape-out data in response to the simulation model for use in production of mask-making-ready tape-out data for use to produce masks and finished chips.
A method for designing a 3D integrated circuit (IC) with two chips stacked on top of each other. The method uses a computer simulation to model the device. The top chip has a substrate with top and bottom surfaces. Two Through-Silicon Vias (TSVs) go completely through the top chip's substrate. The first TSV connects the top surface of the substrate to the bottom surface, suppressing latch-up. This TSV's bottom end is insulated from the chip below. The second TSV connects to a conductive feature on the top of the bottom chip through a via in an insulating layer on the bottom of the top chip's substrate. The method generates tape-out data from the simulation for manufacturing masks and finished chips.
2. The method of claim 1 further comprising generating tape-out data for production of lithographic masks.
The method for designing a 3D integrated circuit (IC) as described above further includes generating tape-out data specifically for creating lithographic masks used in the IC fabrication process. This tape-out data defines the patterns and features that will be etched or deposited onto the silicon wafers during manufacturing. This builds on the previous description involving a first TSV for latch-up suppression and a second TSV for inter-chip connection.
3. The method of claim 1 wherein an opening in the insulating layer on the backside surface of the first substrate exposes both the second end of the first TSV and a particular region of the first substrate on the backside surface thereof.
In the method for designing a 3D integrated circuit (IC) with latch-up suppression using a TSV, as described above, an opening in the insulating layer on the bottom of the top chip's substrate exposes both the bottom end of the first TSV (used for latch-up suppression) and a specific area of the substrate itself on that bottom surface. This arrangement allows for a direct connection or contact to the substrate material in addition to the TSV.
4. The method of claim 3 wherein conductive material in the opening electrically connects the second end of the first TSV with the particular region.
In the method for designing a 3D integrated circuit (IC), where an opening exposes the TSV and substrate, conductive material fills that opening, electrically connecting the bottom end of the first TSV with the exposed region of the substrate. This provides a direct electrical connection between the TSV and the substrate, enhancing the latch-up suppression effect. This builds on the previous descriptions of TSVs going through the substrate and an insulating layer having an opening.
5. The method of claim 1 wherein a plurality of RDL connectors are disposed on the backside of the insulating layer, at least one of the RDL connectors electrically connected to both to the second TSV through the via in the insulating layer, and to the electrically conductive feature on the topside surface of the second chip.
In the method for designing a 3D integrated circuit (IC) with a first TSV for latch-up suppression and a second TSV for inter-chip connection, multiple Redistribution Layer (RDL) connectors are placed on the insulating layer's backside. At least one of these RDL connectors is electrically connected to both the second TSV (through the via in the insulating layer) and the conductive feature on the top surface of the second chip below. This RDL connection helps route signals and power between the chips.
6. An electronic design automation (EDA) system having a processor and a non-transitory computer-readable storage medium that stores software code portions for modeling a three-dimensional integrated circuit device having a first chip superposing a second chip, the first and second chips each having opposite topside and backside surfaces, wherein the software code portions, when executed by a processor, build a software model, the software model: a) defining placement and routing for at least one metal layer on the topside of the first chip, and b) defining placement and routing for at least one metal layer on the topside of the second chip, and c) identifying a position of each of a plurality of TSVs, each TSV extending entirely through the first chip, wherein, in the software model: a transistor is formed in the first chip, a first conductive path electrically connects a first TSV of the plurality on a first end to the first chip topside surface at a first point, and on a second end to the first chip backside surface, thereby suppressing latch-up, the second end of the first TSV being electrically insulated from the second chip, and a second TSV of the plurality forms part of a second conductive path between the at least one metal layer on the topside surface of the first chip and the at least one metal layer on the topside surface of the second chip, and wherein the software code portions generate tape-out data in response to the software model, for use in production of mask-making ready tape-out data for use to produce masks and finished chips.
An Electronic Design Automation (EDA) system is used to model a 3D integrated circuit (IC) with two stacked chips. The software defines the placement of metal layers on the top of both chips and the positions of Through-Silicon Vias (TSVs) that go through the top chip. A transistor is formed in the top chip. The model includes a first TSV connecting the top surface of the top chip to its bottom surface for latch-up suppression, with the bottom end insulated from the chip below. A second TSV forms part of a conductive path between the metal layers on the top of the top and bottom chips. The system generates tape-out data for mask creation and chip production.
7. The system of claim 6 wherein, in the software model, the first conductive path further comprises a conductive material filling a via through an insulating layer on the backside of the first chip.
In the EDA system modeling the 3D IC, the first conductive path (latch-up suppression) includes a conductive material filling a via through an insulating layer on the bottom of the top chip. This provides an electrical connection from the TSV to the backside of the top chip's substrate, enhancing the latch-up suppression mechanism described previously. The overall design includes two chips stacked, TSVs, and metal layers.
8. The system of claim 7 wherein the second conductive path further includes one of a plurality of RDL connectors disposed on the backside of the insulating layer.
In the EDA system modeling the 3D IC with latch-up suppression, the second conductive path (inter-chip connection) includes one of several Redistribution Layer (RDL) connectors placed on the backside of the insulating layer. This RDL connector helps route signals between the TSV and the metal layer on the bottom chip, providing a pathway for inter-chip communication. This extends the earlier description of TSVs, an insulating layer, and vias.
9. The system of claim 6 wherein, in the software model, the first chip comprises a p-type lightly doped substrate, and wherein the first point is on a p-type heavily doped contact pad on the first chip topside surface.
In the EDA system for modeling the 3D IC, the top chip has a lightly doped p-type substrate. The first TSV, which is used for latch-up suppression, connects to the top surface of the top chip at a heavily doped p-type contact pad. This specific doping configuration optimizes the latch-up suppression effect. This refers to the overall system with two chips stacked, TSVs, and metal layers.
10. The system of claim 6 , wherein the storage medium further stores software code portions which, when executed by a processor, simulate an aspect of the three-dimensional integrated circuit device.
The EDA system for modeling a 3D integrated circuit (IC) also includes software that simulates an aspect of the device's performance. This simulation could analyze electrical behavior, thermal characteristics, or other relevant parameters. This simulation step helps verify the design and identify potential issues before fabrication. This simulation complements the earlier described modeling with TSVs and metal layers on stacked chips.
11. An electronic design automation (EDA) system having a processor and a non-transitory computer-readable storage medium storing first software code portions and second software code portions, wherein the first software code portions, when executed by a processor, plan layout of a three-dimensional integrated circuit device implementing an integrated circuit design, the device having a first chip superposing a second chip, the first and second chips each having opposite topside and backside surfaces, the layout identifying: a) at least one metal layer on the topside surface of the first chip, b) at least one metal layer on the topside surface of the second chip, and c) a plurality of TSVs, each TSV extending entirely through the first chip; wherein the second software code portions, when executed by a processor, generate a tape-out data file to define a plurality of masks, the plurality of masks comprising: a) a first mask used to form the at least one metal layer on the topside of the first chip, b) a second mask used to form the at least one metal layer on the topside of the second chip, c) at least one TSV mask identifying a position of each of the plurality of TSVs, and d) at least one mask used to form a transistor is in the first chip, wherein a first conductive path electrically connects a first TSV of the plurality on a first end to the first chip topside surface, and on a second end to the first chip backside surface, thereby suppressing latch-up in the first chip, the second end of the first TSV being electrically insulated from the second chip, and wherein a second TSV of the plurality forms part of a second conductive path between the at least one metal layer on the topside surface of the first chip and the at least one metal layer on the topside surface of the second chip, wherein the tape-out data file is used in production of mask-making-ready tape-out data for use to produce masks and finished chips.
An Electronic Design Automation (EDA) system plans the layout of a 3D integrated circuit (IC) with two chips stacked. The system defines the metal layers on the tops of both chips and the positions of Through-Silicon Vias (TSVs) going through the top chip. The system generates a tape-out data file to define masks for the metal layers, the TSVs, and transistors. A first TSV connects the top surface of the top chip to its bottom surface for latch-up suppression, and its bottom end is insulated from the chip below. A second TSV forms part of a conductive path between the metal layers on the tops of the top and bottom chips. The tape-out data is used to create masks for chip production.
12. The system of claim 11 wherein, in the integrated circuit design, the first conductive path further comprises a conductive material filling a via formed in an insulating layer on the backside of the first chip.
In the EDA system for planning the layout of the 3D IC, the first conductive path (latch-up suppression) includes a conductive material filling a via in an insulating layer on the backside of the top chip. This provides an electrical connection from the TSV to the backside of the top chip's substrate, enhancing the latch-up suppression mechanism. This builds on the described layout planning with metal layers, TSVs, and stacked chips.
13. The system of claim 12 wherein the second conductive path further comprises one of a plurality of RDL connectors disposed on the backside of the insulating layer.
In the EDA system for planning the layout of the 3D IC, the second conductive path (inter-chip connection) includes one of multiple Redistribution Layer (RDL) connectors on the backside of the insulating layer. This RDL connector routes signals between the TSV and the metal layer on the bottom chip, facilitating inter-chip communication. This adds to the previous descriptions of layout planning with metal layers, TSVs, and an insulating layer.
14. The system of claim 13 wherein the second conductive path further comprises a bump contact disposed between the at least one of the plurality of RDL connectors and the metal layer on the topside surface of the second chip.
In the EDA system for planning the 3D IC layout, the second conductive path (inter-chip connection) also includes a bump contact between the RDL connector and the metal layer on the top of the bottom chip. This bump contact provides a reliable electrical connection between the RDL layer and the chip below. This expands the design which already included metal layers, TSVs, RDL connectors, and an insulating layer.
15. The system of claim 11 , wherein the storage medium further stores third software code portions which, when executed by a processor, simulate an aspect of the three-dimensional integrated circuit device.
The EDA system for planning the layout of a 3D integrated circuit (IC) also includes software that simulates an aspect of the device's performance. This simulation can analyze electrical behavior, thermal characteristics, or other parameters. This simulation step helps verify the design and identify potential issues before fabrication. This simulation complements the layout planning described earlier, which includes TSVs and metal layers on stacked chips.
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November 14, 2017
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