Latch-Up Suppression and Substrate Noise Coupling Reduction Through a Substrate Back-Tie for 3d Integrated Circuits

1. A method for designing an integrated circuit device, comprising: using a computer system, providing a simulation model for a three-dimensional integrated circuit device implementing an integrated circuit design, the device having a first chip superposing a second chip, the first chip having a first substrate having opposite topside and backside surfaces and the second chip having opposite topside and backside surfaces, the first chip having an insulating layer on the backside surface of the first substrate, wherein first and second TSVs each extend entirely through the first substrate, wherein a conductive path electrically connects the first TSV on a first end to the first substrate topside surface, and on a second end to the first substrate backside surface, thereby suppressing latch-up in the first chip, the second end of the first TSV being electrically insulated from the second chip, and wherein the second TSV electrically connects through a via in the insulating layer on the backside surface of the first substrate to an electrically conductive feature on the topside surface of the second chip; and generating tape-out data in response to the simulation model for use in production of mask-making-ready tape-out data for use to produce masks and finished chips.

2. The method of claim 1 further comprising generating tape-out data for production of lithographic masks.

3. The method of claim 1 wherein an opening in the insulating layer on the backside surface of the first substrate exposes both the second end of the first TSV and a particular region of the first substrate on the backside surface thereof.

4. The method of claim 3 wherein conductive material in the opening electrically connects the second end of the first TSV with the particular region.

5. The method of claim 1 wherein a plurality of RDL connectors are disposed on the backside of the insulating layer, at least one of the RDL connectors electrically connected to both to the second TSV through the via in the insulating layer, and to the electrically conductive feature on the topside surface of the second chip.

6. An electronic design automation (EDA) system having a processor and a non-transitory computer-readable storage medium that stores software code portions for modeling a three-dimensional integrated circuit device having a first chip superposing a second chip, the first and second chips each having opposite topside and backside surfaces, wherein the software code portions, when executed by a processor, build a software model, the software model: a) defining placement and routing for at least one metal layer on the topside of the first chip, and b) defining placement and routing for at least one metal layer on the topside of the second chip, and c) identifying a position of each of a plurality of TSVs, each TSV extending entirely through the first chip, wherein, in the software model: a transistor is formed in the first chip, a first conductive path electrically connects a first TSV of the plurality on a first end to the first chip topside surface at a first point, and on a second end to the first chip backside surface, thereby suppressing latch-up, the second end of the first TSV being electrically insulated from the second chip, and a second TSV of the plurality forms part of a second conductive path between the at least one metal layer on the topside surface of the first chip and the at least one metal layer on the topside surface of the second chip, and wherein the software code portions generate tape-out data in response to the software model, for use in production of mask-making ready tape-out data for use to produce masks and finished chips.

7. The system of claim 6 wherein, in the software model, the first conductive path further comprises a conductive material filling a via through an insulating layer on the backside of the first chip.

8. The system of claim 7 wherein the second conductive path further includes one of a plurality of RDL connectors disposed on the backside of the insulating layer.

9. The system of claim 6 wherein, in the software model, the first chip comprises a p-type lightly doped substrate, and wherein the first point is on a p-type heavily doped contact pad on the first chip topside surface.

10. The system of claim 6 , wherein the storage medium further stores software code portions which, when executed by a processor, simulate an aspect of the three-dimensional integrated circuit device.

11. An electronic design automation (EDA) system having a processor and a non-transitory computer-readable storage medium storing first software code portions and second software code portions, wherein the first software code portions, when executed by a processor, plan layout of a three-dimensional integrated circuit device implementing an integrated circuit design, the device having a first chip superposing a second chip, the first and second chips each having opposite topside and backside surfaces, the layout identifying: a) at least one metal layer on the topside surface of the first chip, b) at least one metal layer on the topside surface of the second chip, and c) a plurality of TSVs, each TSV extending entirely through the first chip; wherein the second software code portions, when executed by a processor, generate a tape-out data file to define a plurality of masks, the plurality of masks comprising: a) a first mask used to form the at least one metal layer on the topside of the first chip, b) a second mask used to form the at least one metal layer on the topside of the second chip, c) at least one TSV mask identifying a position of each of the plurality of TSVs, and d) at least one mask used to form a transistor is in the first chip, wherein a first conductive path electrically connects a first TSV of the plurality on a first end to the first chip topside surface, and on a second end to the first chip backside surface, thereby suppressing latch-up in the first chip, the second end of the first TSV being electrically insulated from the second chip, and wherein a second TSV of the plurality forms part of a second conductive path between the at least one metal layer on the topside surface of the first chip and the at least one metal layer on the topside surface of the second chip, wherein the tape-out data file is used in production of mask-making-ready tape-out data for use to produce masks and finished chips.

12. The system of claim 11 wherein, in the integrated circuit design, the first conductive path further comprises a conductive material filling a via formed in an insulating layer on the backside of the first chip.

13. The system of claim 12 wherein the second conductive path further comprises one of a plurality of RDL connectors disposed on the backside of the insulating layer.

14. The system of claim 13 wherein the second conductive path further comprises a bump contact disposed between the at least one of the plurality of RDL connectors and the metal layer on the topside surface of the second chip.

15. The system of claim 11 , wherein the storage medium further stores third software code portions which, when executed by a processor, simulate an aspect of the three-dimensional integrated circuit device.