Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A shared cache memory system, comprising: a main controller; a first memory unit mounted on a bus; a first cache manager coupled to the first memory unit; a first set of sub-memory units coupled to the first cache manager; a first set of sub-processing elements coupled to the first set of sub-memory units; and a second cache manager coupled to an input and an output of a second memory unit mounted on the bus, the first cache manager: receiving instructions to mount the first set of sub-memory units to the second memory unit, responsive to a diagnosis on the first memory unit by the main controller, from the main controller in response to a cache miss at the first set of sub-memory units; receiving a request for memory content originating from the first set of sub-processing elements; isolating the first memory unit from the first set of sub-memory units and the first set of sub-processing elements by: wrapping an input and an output of the first memory unit; bypassing the first memory unit; configuring mounting of the first cache manager based on the received mounting instructions; and arranging the input and the output of the first memory unit to allow sharing to the second memory unit of requests made to the first memory unit; and sharing the request for memory content to the input of the second memory unit via the second cache manager to enable the second memory unit to function as a next-level higher cache to the first memory unit in the case that the first set of sub-memory units experience a cache miss, the first memory unit exhibits a yield below a predetermined threshold, and the first set of sub-memory units and the first set of sub-processing elements are operational, wherein the main controller is coupled at a top of a hierarchy on the bus and in communication with the first and second cache managers and the second cache manager directs the request to the input of the second memory unit to enable a search of the second memory unit and a second set of sub-memory units coupled to the second memory unit.
A shared cache memory system improves performance in multi-core processors by allowing cores to share cache units. The system consists of a main controller, a first memory unit, a first cache manager, sub-memory units, and sub-processing elements. If the main controller detects a problem with the first memory unit (e.g., low yield, cache miss), the first cache manager, upon receiving instructions from the main controller, isolates the failing first memory unit by wrapping/bypassing it. The first cache manager then configures the system to route memory requests from the first set of sub-processing elements directly to a second memory unit (via a second cache manager). This allows the second memory unit to act as a higher-level cache for the first set of sub-processing elements, improving performance by sharing cache resources. The main controller is at the top of a hierarchy and communicates with both cache managers. The second cache manager directs the request to the input of the second memory unit to enable a search of the second memory unit and its sub-memory units.
2. The shared cache memory system of claim 1 , the first memory unit and the second memory unit comprising virtualized cache memory units.
A shared cache memory system is designed to improve data access efficiency in computing environments where multiple processing units require fast access to shared data. The system addresses the challenge of managing cache memory resources in a way that reduces redundancy, minimizes latency, and optimizes performance. The system includes a shared cache memory that is divided into multiple memory units, where at least two of these units are virtualized cache memory units. Virtualization allows these units to be dynamically allocated, reconfigured, or shared among different processing elements or tasks, enhancing flexibility and resource utilization. The virtualized cache memory units can be assigned to different processes, applications, or hardware components as needed, enabling efficient use of available cache resources. This approach helps prevent cache thrashing, reduces conflicts, and improves overall system throughput by ensuring that frequently accessed data is stored in the most accessible and efficient manner. The system may also include mechanisms to manage cache coherence, ensuring that data consistency is maintained across the virtualized units. By leveraging virtualization, the system adapts to varying workload demands, improving performance in multi-core, multi-threaded, or distributed computing environments.
3. The shared cache memory system of claim 1 , the second cache manager being further operable to receive an additional request, and share the additional request to at least one of the following: the first memory unit; or a third memory unit.
In the shared cache memory system described in Claim 1, the second cache manager can handle additional memory requests. After a first cache miss occurs at the first memory unit, the second cache manager may subsequently receive a second request, which it can route to either the first memory unit (if it has recovered) or to a third memory unit to improve cache performance or fault tolerance. The main controller, first memory unit, first cache manager, sub-memory units, sub-processing elements, second memory unit, and second cache manager, along with a third memory unit, cooperate to manage cache misses and improve performance.
4. The shared cache memory system of claim 1 , a second set of sub-processing elements being coupled to the second set of sub-memory units.
The shared cache memory system described in Claim 1 includes a second set of sub-processing elements connected to the second set of sub-memory units managed by the second cache manager. If the first memory unit has low yield or a cache miss occurs, the first cache manager isolates it and shares requests to the second memory unit. Both the first and second sets of sub-processing elements can then benefit from using the second memory unit as a higher-level cache. The main controller, first memory unit, first cache manager, sub-memory units, sub-processing elements, second memory unit, second cache manager, and second set of sub-processing elements work together.
5. The shared cache memory system of claim 1 , the bus being coupled to the main controller.
In the shared cache memory system described in Claim 1, the bus, which connects the various memory units and cache managers, is also directly connected to the main controller. This direct connection allows the main controller to efficiently monitor and control the entire cache system, including detecting memory unit failures and instructing cache managers to reroute memory requests. The main controller, first memory unit, first cache manager, sub-memory units, sub-processing elements, second memory unit, and second cache manager are interconnected by a bus under the control of the main controller.
6. The shared cache memory system of claim 1 , the first cache manager further sharing the request when the first memory unit is inoperable.
In the shared cache memory system described in Claim 1, the first cache manager will share the memory request with the second memory unit if the first memory unit is entirely inoperable. This extends the fault-tolerance by allowing the second cache to still serve the first set of sub-processing elements even if their primary cache has completely failed. The main controller, first memory unit, first cache manager, sub-memory units, sub-processing elements, second memory unit, and second cache manager work together to provide this fault-tolerant cache sharing.
7. The shared cache memory system of claim 1 , the first cache manager being coupled to an input and an output of the first memory unit.
In the shared cache memory system described in Claim 1, the first cache manager is connected to both the input and output of the first memory unit. This allows the first cache manager to completely wrap the first memory unit and control all data flow to and from it, enabling isolation and bypass when the first memory unit exhibits low yield or fails. The first cache manager is central to rerouting memory requests to the second memory unit. The main controller, first memory unit, first cache manager, sub-memory units, sub-processing elements, second memory unit, and second cache manager work together for cache sharing and fault tolerance.
8. A shared cache memory system, comprising: a first cache memory unit mounted on a bus; a first cache manager coupled to an input and an output of the first cache memory unit; a first set of sub-cache memory units coupled to the first cache manager; a second cache memory unit mounted on the bus; a second cache manager coupled to an input and an output of the second cache memory unit; and a second set of sub-cache memory units coupled to the second cache manager, the first cache manager: receiving instructions to mount the first set of sub-cache memory units to the second cache memory unit, responsive to a diagnosis on the first cache memory unit by a main controller, from the main controller in response to a cache miss at the first set of sub-cache memory units; receiving a request for memory content originating from a first set of sub-processing elements; isolating the first cache memory unit from the first set of sub-cache memory units by: wrapping an input and an output of the first cache memory unit; bypassing the first cache memory unit; configuring mounting of the first cache manager based on the received mounting instructions; and arranging the input and the output of the first cache memory unit to allow sharing to the second cache memory unit of requests made to the first cache memory unit; and sharing the request for memory content with the input of the second cache memory unit via the second cache manager to enable the second cache memory unit to function as a next-level higher cache to the first cache memory unit in the case that the first set of sub-cache memory units experience a cache miss, the first cache memory unit exhibits a yield below a predetermined threshold, and the first cache memory unit is coupled to an operational first set of sub-cache memory units, wherein the main controller is coupled at a top of a hierarchy on the bus and in communication with the first and second cache managers and the request is received from the second cache manager at an input of the second cache memory unit and the second set of sub-cache memory units.
A shared cache memory system includes two cache memory units (first and second), each with a corresponding cache manager, and sets of sub-cache memory units. The system shares cache when the first cache memory unit performs poorly. The first cache manager isolates the first cache memory unit by wrapping/bypassing its input/output, upon receiving instructions from a main controller to mount the first set of sub-cache memory units to the second cache memory unit in response to a cache miss at the first set of sub-cache memory units and diagnosis on the first cache memory unit by the main controller. Memory requests from a first set of sub-processing elements are then rerouted through the second cache manager to the second cache memory unit. The second cache unit effectively becomes a higher-level cache for the first, improving performance. The main controller communicates with both cache managers and the request is received from the second cache manager at an input of the second memory unit and the second set of sub-memory units.
9. The shared cache memory system of claim 8 , further comprising a first set of sub-processing elements coupled to the first set of sub-cache memory units.
The shared cache memory system described in Claim 8 also has a first set of sub-processing elements that are connected to the first set of sub-cache memory units. These sub-processing elements generate the memory requests that may be rerouted to the second cache memory unit if the first cache memory unit is underperforming, as determined by the main controller instructing the first cache manager to mount the sub-cache memory units to the second cache memory unit in response to a cache miss at the first set of sub-cache memory units and diagnosis on the first cache memory unit.
10. The shared cache memory system of claim 8 , further comprising a second set of sub-processing elements coupled to the second set of sub-cache memory units.
The shared cache memory system described in Claim 8 also includes a second set of sub-processing elements connected to a second set of sub-cache memory units. These sub-processing elements use the second cache memory unit normally, but the second cache memory unit can also act as a higher-level cache for the first set of sub-processing elements if the first cache memory unit is underperforming, as determined by the main controller instructing the first cache manager to mount the sub-cache memory units to the second cache memory unit in response to a cache miss at the first set of sub-cache memory units and diagnosis on the first cache memory unit.
11. The shared cache memory system of claim 8 , the bus being coupled to the main controller.
In the shared cache memory system described in Claim 8, the bus connecting the cache memory units is also connected to the main controller. This allows the main controller to directly monitor the system and instruct the cache managers to reroute memory requests when necessary. The main controller plays a central role in detecting performance issues and coordinating cache sharing.
12. A cache memory sharing method, comprising: receiving a first request on a first cache manager, the first cache manager being coupled to a first memory unit, the first memory unit being coupled to a bus; receiving instructions to mount a first set of sub-cache memory units to a second cache memory unit, responsive to a diagnosis on the first memory unit by a main controller, from the main controller in response to a cache miss at the first set of sub-memory units coupled to the first cache manager; isolating the first memory unit from the first set of sub-memory units by: wrapping an input and an output of the first memory unit; bypassing the first memory unit; configuring mounting of the first cache manager based on the received mounting instructions; and arranging the input and the output of the first memory unit to allow sharing to the second memory unit of requests made to the first memory unit; and sharing the request with the second memory unit by sending the request to a second cache manager in the case that a first set of sub-processing elements coupled to the first memory unit experiences a cache miss, the first memory unit exhibits a yield below a predetermined threshold, and the first set of sub-processing elements are operational, wherein the main controller is coupled at a top of a hierarchy on the bus and in communication with the first and second cache managers and the request is received from the second cache manager at an input of the second memory unit and a second set of sub-cache memory units, the second cache manager being coupled to the second memory unit, the second memory unit being coupled to the bus, and the bus being coupled to the main controller.
A cache memory sharing method reroutes memory requests when a cache unit performs poorly. It begins with a first cache manager receiving a request. If a first memory unit has low yield or a cache miss occurs at the first set of sub-memory units coupled to the first cache manager, the main controller instructs the first cache manager to mount the first set of sub-cache memory units to the second cache memory unit in response to a diagnosis on the first memory unit by the main controller. The first cache manager isolates the failing first memory unit. The request is then sent to a second cache manager associated with a second memory unit. The second memory unit effectively acts as a higher-level cache for the original request. The main controller is at the top of a hierarchy and in communication with the first and second cache managers. The request is received from the second cache manager at an input of the second memory unit and a second set of sub-cache memory units.
13. The cache memory sharing method of claim 12 , the first request being received from the first set of sub-memory units coupled to the first memory unit.
In the cache memory sharing method described in Claim 12, the initial memory request received by the first cache manager comes from the first set of sub-memory units coupled to the first memory unit. These sub-memory units are the initial source of the memory access that triggers the potential cache sharing mechanism if the main controller instructs the first cache manager to mount the first set of sub-cache memory units to the second cache memory unit in response to a diagnosis on the first memory unit and a cache miss at the first set of sub-memory units coupled to the first cache manager.
14. The cache memory sharing method of claim 12 , further comprising: receiving a second request on the second cache manager; and sharing the second request by sending the second request from the second cache manager to at least one of the following: the first cache manager; or a third cache manager.
In the cache memory sharing method described in Claim 12, after the second cache manager receives a request and potentially acts as a higher-level cache, it can also receive a second, independent request. The second cache manager can then forward this second request to either the first cache manager (potentially if the first memory unit has recovered) or to a third cache manager for further processing. The main controller, first cache manager, and second cache manager (potentially along with a third) coordinate cache access.
15. The cache memory sharing method of claim 13 , the second request being received from a second set of sub-memory units coupled to the second memory unit.
In the cache memory sharing method described in Claim 13, the second request received by the second cache manager originates from a second set of sub-memory units, coupled to the second memory unit. The initial request originates from the first set of sub-memory units coupled to the first memory unit. If the first memory unit experiences a cache miss, the main controller can instruct the first cache manager to mount the first set of sub-cache memory units to the second cache memory unit, allowing them to use the second memory unit as a higher-level cache.
16. The cache memory sharing method of claim 15 , the first memory unit, the first set of sub-memory units, the second memory unit, and the second set of sub-memory units being cache memory units.
In the cache memory sharing method described in Claim 15, the first memory unit, first set of sub-memory units, second memory unit, and second set of sub-memory units are all cache memory units. This clarifies that the sharing occurs between different levels or parts of a cache hierarchy, where the first and second memory units and their respective sub-units are all parts of the cache system and the main controller can instruct the first cache manager to mount the first set of sub-cache memory units to the second cache memory unit in response to a diagnosis on the first memory unit.
17. The cache memory sharing method of claim 12 , further comprising sending a response to the first request from the second memory unit to an originator of the request.
In the cache memory sharing method described in Claim 12, after the second memory unit processes the initial request (which was rerouted due to a potential issue with the first memory unit), the second memory unit sends a response back to the originator of the request. This ensures that the requesting sub-processing element receives the data it needs, even though the request was handled by a different cache unit than initially intended after the main controller instructed the first cache manager to mount the first set of sub-cache memory units to the second cache memory unit.
18. The cache memory sharing method of claim 17 , the response being sent via the second cache manager.
In the cache memory sharing method described in Claim 17, the response from the second memory unit to the originator of the request is sent via the second cache manager. This means the second cache manager not only receives and processes the rerouted request, but also handles the return path for the data, ensuring consistent communication after the main controller instructs the first cache manager to mount the first set of sub-cache memory units to the second cache memory unit.
19. The shared cache memory system of claim 1 , the first and second cache managers having a status stored in a memory of the first and second cache managers.
In the shared cache memory system described in Claim 1, the first and second cache managers each have a memory section that stores their status. This allows tracking of their operational state, which may include information about active requests, cache hit/miss rates, and potential error conditions. This status information helps the main controller in making decisions about rerouting requests and managing the overall cache system after the controller makes diagnosis.
20. The shared cache memory system of claim 1 , the first cache manager performing the following cache operation steps: wrapping an input and an output of the first memory unit; configuring bypassing of the first memory unit; configuring mounting information for the first set of sub-memory units; and arranging input and output for the first set of sub-memory units for sharing.
In the shared cache memory system described in Claim 1, the first cache manager performs specific steps to isolate a failing first memory unit and prepare for cache sharing, these include: wrapping the input and output of the first memory unit to control data flow, configuring the system to bypass the first memory unit, configuring mounting information for the first set of sub-memory units to be routed to the second memory unit, and arranging the input and output of the first set of sub-memory units to enable request sharing. These steps are initiated after the main controller detects a problem with the first memory unit.
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November 21, 2017
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