Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An integrated circuit comprising: multiple clock cells of a first type having a first keep-out region, the first type having a first power-usage density; multiple clock cells of a second type having a second keep-out region, the second type having a second power-usage density, the first and the second power-usage densities being different, a higher of the first and second power-usage densities having a larger keep-out region than a lower of the first and second power-usage densities; and a layout of the multiple clock cells of the first type and the second type on the integrated circuit, the layout separating the multiple clock cells of the first type and second type such that the respective keep-out regions of the respective clock cells do not overlap.
An integrated circuit has multiple clock cells. Clock cells of a first type have a first "keep-out region" and a first power usage density. Clock cells of a second type have a second, different, "keep-out region" and a second power usage density. The "keep-out region" is larger for the cell type with the higher power usage density. The clock cells are arranged on the integrated circuit such that the "keep-out regions" of different clock cells do not overlap each other, reducing heat and IR droop.
2. The integrated circuit of claim 1 , wherein the first and second keep-out regions have sizes proportional to the first and second power-usage densities, respectively.
The integrated circuit from the previous description has "keep-out regions" that are sized proportionally to the power usage densities of the clock cell types they surround. This means a clock cell with twice the power usage density will have a "keep-out region" twice the size, helping to manage thermal and electrical effects more effectively.
3. The integrated circuit of claim 1 , wherein the clock cells of the first type are rectangular and the first keep-out region is a rectangle surrounding each of the clock cells of the first type.
In the integrated circuit from the first description, the clock cells of the first type are rectangular in shape, and the corresponding "keep-out region" is also a rectangle that surrounds each of these clock cells. This creates a uniform spacing around each cell.
4. The integrated circuit of claim 1 , wherein the first keep-out region has same width spacings and height spacings, the width spacings having a distance from each of two width borders of the clock cells of the first type and the height spacings having a distance from each of two height borders of the clock cells of the first type.
In the integrated circuit from the first description, the first "keep-out region" has uniform width and height spacings from the clock cells of the first type. The width spacing maintains a constant distance from each of the two width borders, and the height spacing maintains a constant distance from each of the two height borders of the clock cells.
5. The integrated circuit of claim 1 , wherein the first keep-out region is formed as a free-corner keep-out region, the free-corner keep-out region having width and height spacings from width and height borders of the clock cells of the first type.
In the integrated circuit from the first description, the first "keep-out region" is implemented as a "free-corner keep-out region". This means that the "keep-out region" defines spacing from the width and height borders of the clock cells, but the corners are not specifically constrained beyond those width and height constraints.
6. The integrated circuit of claim 1 , wherein the first keep-out region is formed as a half-corner keep-out region, the half-corner keep-out region having width and height spacings from width and height borders of the clock cells of the first type and a half-corner spacing bounded by edges of the width and height spacings nearest a corner of the clock cells of the first type and a line from end points of the edges of the width and height spacings.
In the integrated circuit from the first description, the first "keep-out region" is a "half-corner keep-out region". This type of region defines spacing from the width and height borders of the clock cells. The area near the corner is bounded by the edges of the width and height spacings and a straight line connecting the endpoints of those edges, effectively creating a chamfered corner in the "keep-out region."
7. The integrated circuit of claim 1 , wherein the first keep-out region is formed as a curved-corner keep-out region, the curved-corner keep-out region having width and height spacings from width and height borders of the clock cells of the first type and a curved-corner spacing bounded by edges of the width and height spacings nearest a corner of the clock cells of the first type and a curved, convex line from end points of the edges of the width and height spacings.
In the integrated circuit from the first description, the first "keep-out region" is a "curved-corner keep-out region." This region defines spacing from the width and height borders of the clock cells. The corner spacing is bounded by the edges of the width and height spacings and a curved, convex line connecting the endpoints of those edges, creating a rounded corner in the "keep-out region."
8. The integrated circuit of claim 7 , wherein the curved, convex line is an arc from the end points of the edges of the width and height spacings.
In the integrated circuit with "curved-corner keep-out regions" from the previous description, the curved, convex line that forms the corner of the "keep-out region" is specifically an arc. This arc connects the end points of the width and height spacing edges, creating a circular rounded corner.
9. The integrated circuit of claim 1 , wherein the first keep-out region has a power-usage density less than the first power-usage density and the second keep-out region has a power-usage density less than the second power-usage density.
In the integrated circuit from the first description, the "keep-out region" itself is considered to have a power usage density that is less than the power usage density of the clock cell it surrounds. This is due to the larger area and the absence of active components.
10. The integrated circuit of claim 1 , wherein sizes of the first keep-out region and the second keep-out region are selected based on target power-usage densities which avoid negative thermal effects caused by the first and second power-usage densities.
In the integrated circuit from the first description, the sizes of the "keep-out regions" are determined based on target power-usage densities. These target densities are chosen to prevent negative thermal effects, like hotspots, or IR droop (voltage drop) caused by the power usage densities of the clock cells. The goal is to maintain a safe and reliable operating environment for the IC.
11. A placement system comprising: one or more computer processors; one or more computer-readable media having instructions that, responsive to execution by the one or more computer processors, implements a placement manager, the placement manager configured to: receive, for a first type of clock cell, a first keep-out region; receive, for a second type of clock cell, a second keep-out region having a different size than the first keep-out region; and place in an integrated circuit the first type of clock cell and the second type of clock cell without overlap of the first keep-out region and the second keep-out region.
A placement system for integrated circuits uses one or more processors and memory to implement a "placement manager". This manager receives a first "keep-out region" for a first type of clock cell and a second "keep-out region" for a second type of clock cell (the regions have different sizes). The manager then arranges these clock cells on the IC such that the "keep-out regions" around the clock cells do not overlap.
12. The placement system of claim 11 , wherein the placement manager is further configured to determine, based on a power-usage density of the first type of clock cell and a power-usage density of the second type of clock cell, the first keep-out region and the second keep-out region, respectively.
The placement system from the previous description includes a "placement manager" that determines the size of the first and second "keep-out regions" based on the power-usage densities of the corresponding first and second types of clock cells. The higher the power-usage density, the larger the "keep-out region".
13. The placement system of claim 12 , wherein the placement manager is further configured to determine, prior to determination of the first and second keep-out regions, the power-usage densities of the first and second types of clock cells.
In the placement system from the previous description, the "placement manager" first determines the power-usage densities of the first and second types of clock cells. Only after determining these densities does it calculate the sizes of the first and second "keep-out regions".
14. The placement system of claim 11 , wherein the placement manager is further configured to place a data cell within the first keep-out region or the second keep-out region.
In the placement system from the first description, the "placement manager" is also capable of placing a standard data cell *inside* a "keep-out region" around a clock cell. This allows for denser layouts by utilizing the space defined by the "keep-out region" for non-clock-related cells.
15. The placement system of claim 14 , wherein the first keep-out region has a first width spacing and a first height spacing and the second keep-out region has a second width spacing and second height spacing, and wherein placement by the placement manager places the first type of clock cell and the second type clock cell at least a sum of the first width spacing and the second width spacing or the first height spacing and the second height spacing.
In the placement system with "keep-out regions" from the previous descriptions, the first "keep-out region" has a first width spacing and a first height spacing, and the second "keep-out region" has a second width spacing and a second height spacing. The "placement manager" ensures that the minimum distance between the first and second clock cells is at least the *sum* of their respective width spacings or the sum of their respective height spacings, guaranteeing no overlap of the "keep-out regions."
16. The placement system of claim 11 , wherein the first keep-out region or the second keep-out region is a free-corner keep-out region, a half-corner keep-out region, a curved-corner keep-out region, a rectangular keep-out region, a flexible-spacing keep-out region, or a balloon keep-out region.
In the placement system from the first description, the "keep-out regions" can be of various shapes: "free-corner", "half-corner", "curved-corner", "rectangular", "flexible-spacing", or "balloon". These different shapes allow for fine-tuning the placement based on specific design requirements and thermal considerations.
17. An integrated circuit comprising: a clock-cell layout, the clock-cell layout based on respective power-usage densities of multiple clock cell types in the integrated circuit, the clock-cell layout having: a first keep-out region associated with clock cells of a first type, the first type having a first power-usage density; a second keep-out region associated with clock cells of a second type, the second type having a second power-usage density; and a third keep-out region associated with clocks cells of a third type, the third type having a third power-usage density, the first power-usage density higher than the second power-usage density, the second power-usage density higher than the third power-usage density, the first keep-out region representing an average of a total of multiple flexible keep-out regions around each of the clocks cells of the first type, the second keep-out region representing an average of a total of multiple flexible keep-out regions around each of the clocks cells of the second type, the third keep-out region representing an average of a total of multiple flexible keep-out regions around each of the clocks cells of the third type, and the first keep-out region being larger than the second keep-out region and the second keep-out region being larger than the third keep-out region.
An integrated circuit includes a clock-cell layout that is based on the power-usage densities of multiple clock cell types. A first type of clock cell with a first power-usage density has a first "keep-out region." A second type with a second power-usage density has a second "keep-out region." A third type with a third power-usage density has a third "keep-out region." The power-usage densities decrease from first to second to third type, and correspondingly, the sizes of the "keep-out regions" also decrease from first to second to third. The keep-out regions represent the average of multiple flexible keep-out regions around each of the clock cells of each type.
18. The integrated circuit of claim 17 , wherein the first, second, and third keep-out regions surround each of the respective clock cells.
In the integrated circuit from the previous description, the first, second, and third "keep-out regions" completely surround each of the respective clock cells. The keep-out regions create a buffer zone on all sides of the clock cell.
19. The integrated circuit of claim 17 , wherein the first, second, and third keep-out regions vary in a width or height dimension but are of a fixed area.
In the integrated circuit from the previous description, the first, second, and third "keep-out regions" can vary in their width or height dimensions, but they all maintain the same total area. This allows for adjusting the shape of the "keep-out region" while maintaining a consistent amount of reserved space.
20. The integrated circuit of claim 17 , wherein the integrated circuit comprises a microprocessor, a graphical processing unit (GPU), a memory array, or a modem, and wherein the clock-cell layout is within a portion of the microprocessor, the GPU, the memory array, or the modem.
The integrated circuit with power-density based clock cell layout from the previous description can be a microprocessor, a GPU, a memory array, or a modem. The clock-cell layout with "keep-out regions" is used within a portion of one of these components.
21. The integrated circuit of claim 17 , wherein the first keep-out region being larger than the second keep-out region and the second keep-out region being larger than the third keep-out region is by having a larger width spacing, height spacing, or area.
In the integrated circuit layout from the previous description, the differences in the sizes of the first, second, and third "keep-out regions" (first > second > third) are achieved by having larger width spacings, larger height spacings, or a larger overall area for the "keep-out regions" with higher power-usage densities.
22. A method for placing cells in an integrated circuit, executable by a placement system, the method comprising: receiving or determining, for a first type of clock cell, a first keep-out region; receiving or determining, for a second type of clock cell, a second keep-out region having a different size than the first keep-out region; and placing the first type of clock cell and the second type of clock cell without overlap of the first keep-out region and the second keep-out region.
A method for placing cells in an integrated circuit, performed by a placement system, involves receiving or determining a first "keep-out region" for a first type of clock cell and receiving or determining a second, different-sized "keep-out region" for a second type of clock cell. The method then places the clock cells such that the "keep-out regions" do not overlap.
23. The method of claim 22 , wherein the receiving or determining the first keep-out region and the second keep-out region determines the first and second keep-out regions, the first keep-out region determined based on a power-usage density of the first type of clock cell and the second keep-out region determined based on a power-usage density of the second type of clock cell.
The method from the previous description determines the first and second "keep-out regions" based on the power-usage densities of the corresponding first and second types of clock cells. Specifically, the size of each "keep-out region" is a function of the power-usage density of the clock cell it surrounds.
24. The method of claim 23 , wherein the power-usage density approximates potential thermal output.
In the method from the previous description, the power-usage density is used as an approximation of the potential thermal output (heat) of the clock cell. A higher power-usage density indicates a greater potential for generating heat.
25. The method of claim 23 , wherein the power-usage density approximates potential IR droop.
In the method that determines "keep-out regions" based on power usage from prior claim, the power-usage density is an approximation of the potential IR droop (voltage drop) caused by the clock cell's operation. Higher density indicates higher IR droop potential.
26. The method of claim 23 , further comprising determining, prior to determining the first and second keep-out regions, the power-usage density of the first type and second type of clock cells.
In the method from the previous descriptions, the power-usage density of each clock cell type is determined *before* the corresponding "keep-out region" is calculated. This ensures the "keep-out region" is appropriately sized for the cell's power characteristics.
27. The method of claim 22 , wherein the first keep-out region and the second keep-out region are spacings in a plane surrounding the first type and second type of clock cells, respectively, and have a width and a height spacing from borders of the first type and second type of clock cells, respectively.
In the cell placement method from the first description, the "keep-out regions" are defined as spacings in a plane around the clock cells, with a defined width and height spacing from the borders of the respective clock cells.
28. The method of claim 27 , wherein the first keep-out region has a first width spacing and a first height spacing and the second keep-out region has a second width spacing and second height spacing, and wherein placing the first type of clock cell and the second type clock cell spaces the first type of clock cell at least a sum of the first width spacing and the second width spacing or the first height spacing and the second height spacing from the second clock cell.
In the cell placement method with width and height spacings, the first "keep-out region" has a first width spacing and a first height spacing, and the second "keep-out region" has a second width spacing and a second height spacing. The method places the first and second clock cells such that they are separated by at least the sum of the first and second width spacings *or* the sum of the first and second height spacings.
29. The method of claim 22 , wherein the first keep-out region has a power-usage density less than the a power-usage density of the first type of clock cell, and the second keep-out region has a power-usage density less than a power-usage density of the second type of clock cell.
In the method for clock cell placement, the power-usage density *within* the "keep-out region" is less than the power-usage density of the clock cell it surrounds. Essentially, the keep-out region contributes less power usage per unit area.
30. The method of claim 22 , wherein sizes of the first keep-out region and the second keep-out region are selected based on target power-usage densities which avoid negative thermal effects caused by power-usage densities of the first type and second type of clock cells.
In the method for placing clock cells and determining "keep-out regions", the sizes of the "keep-out regions" are chosen based on target power-usage densities. These target densities are selected to avoid negative thermal effects (hotspots) or IR droop caused by the power-usage densities of the clock cells.
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November 21, 2017
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