Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A secure digital input/output (SDIO) system comprising: a single SDIO interface adapted to be connected to a host; a single SDIO bus connected to the SDIO interface; a first SDIO unit connected to the SDIO bus; a second SDIO unit connected to the SDIO bus; wherein the first SDIO unit and the second SDIO unit are configured to receive a single multiple SDIO (MSDIO) command from the host requiring both the first SDIO unit and the second SDIO unit to both send data back to the host using the single SDIO bus; a first arbitration logic in the first SDIO unit; and a second arbitration logic in the first SDIO unit, wherein the first arbitration logic and the second arbitration logic are configured to determine when the first SDIO unit and when the second SDIO unit has access to the single SDIO bus to avoid interference on the single SDIO bus.
A system allows a host device to communicate with multiple SDIO devices (like memory cards or peripherals) using a single SDIO interface and bus. Two SDIO units share the same SDIO bus. A single "multiple SDIO" (MSDIO) command from the host triggers both SDIO units to send data back to the host via the shared bus. Each SDIO unit contains arbitration logic (a decision-making circuit) that coordinates access to the SDIO bus, preventing data collisions. This arbitration logic determines when each unit can transmit to avoid interference on the single SDIO bus.
2. The SDIO system of claim 1 wherein the single MSDIO command is an SDIO CMD53 command.
The MSDIO command sent to multiple SDIO units (as described in the previous system) is specifically an SDIO CMD53 command, which is a standard SDIO command used for data transfer. The system utilizes this command to initiate simultaneous data transmission from multiple SDIO units over a single SDIO bus.
3. The SDIO system of claim 1 wherein the host is unaware that the single MSDIO command is to cause both the first SDIO unit and the second SDIO unit to send data the host.
In this SDIO system with multiple devices sharing a single SDIO interface, the host device sends a single MSDIO command to trigger data transfer from two SDIO units. Critically, the host is *unaware* that this single command is causing *both* SDIO units to respond and transmit data. The SDIO units manage the simultaneous data transfer transparently to the host.
4. The SDIO system of claim 1 wherein the first arbitration logic further comprises: a finite state machine (FSM) configured to at least partially determine when the first SDIO unit has access to the single SDIO bus and when the second SDIO unit has access to the single SDIO bus.
The arbitration logic within each SDIO unit (responsible for controlling bus access) includes a finite state machine (FSM). This FSM is a digital logic circuit that uses states and transitions to determine when its SDIO unit can access the shared SDIO bus. The FSM helps to manage the timing and sequencing of bus access requests and grants, ensuring that data transmissions from multiple SDIO units do not collide.
5. The SDIO system of claim 3 wherein the first arbitration logic further comprises: a software (SW) driver configured to coordinate with the FSM to determine arbitration of the SDIO bus.
The arbitration logic within each SDIO unit uses a software (SW) driver in addition to the finite state machine. The SW driver interacts with the FSM to determine how the single SDIO bus is arbitrated. The software driver likely provides a higher-level control and configuration interface for the arbitration process, allowing for more flexible and dynamic bus management.
6. The SDIO system of claim 1 wherein the first arbitration logic and the second arbitration logic are identical.
The arbitration logic in the first SDIO unit is identical to the arbitration logic in the second SDIO unit. Both units use the same hardware and software implementation to determine when they can access the shared SDIO bus, ensuring a consistent and fair arbitration process.
7. The SDIO system of claim 1 wherein the first arbitration logic and the second arbitration logic arbitrate the single SDIO bus without host intervention or knowledge of the arbitration of the single SDIO bus.
The arbitration of the single SDIO bus, handled by the first and second arbitration logic, happens without any intervention from the host device and the host is not even aware of how the single SDIO bus is being arbitrated. This offloads the arbitration complexity from the host and allows the SDIO units to autonomously manage bus access.
8. The SDIO system of claim 1 wherein the first arbitrator logic is configured to access to the single SDIO bus based, at least in part, on an amount of data available in the first SDIO unit and an amount of data available in the second SDIO unit.
The arbitration logic considers the amount of data each SDIO unit has available when deciding which unit gets access to the SDIO bus. The logic grants bus access based, at least in part, on data volume in first and second SDIO units. This allows the system to prioritize units with more data to send, improving overall throughput and efficiency.
9. The SDIO system of claim 1 wherein the first SDIO unit is configured to build frames of data with a frame size.
The first SDIO unit constructs data frames of a specific size before sending data over the SDIO bus. The data is packaged into frames of a specific, predetermined size, which improves data management and error handling during transmission.
10. The SDIO system of claim 1 wherein the first SDIO unit and the second SDIO are formed on a same semiconductor chip.
The first and second SDIO units are physically located on the same semiconductor chip. This integration can reduce the physical size of the system, reduce the distance between the units (improving signal integrity), and potentially lower manufacturing costs.
11. The SDIO system of claim 9 wherein the first SDIO unit further comprises: a framing logic configured to collected data and build the frames of data.
The first SDIO unit has framing logic for assembling data frames with frame size (as described in the previous system). This framing logic collects the raw data and assembles it into the structured frames that are then sent over the SDIO bus.
12. The SDIO system of claim 9 wherein the first SDIO unit further comprises: a frame first-in first-out (FIFO) buffer configured to store the frames of data.
The first SDIO unit contains a frame first-in, first-out (FIFO) buffer for storing the data frames described above. The FIFO buffer temporarily holds the assembled data frames before they are transmitted over the SDIO bus, allowing the SDIO unit to manage data flow and timing.
13. The SDIO system of claim 11 wherein the framing logic is configured to mark frames with an ID and schedule them for later autonomous transmission to the host.
The framing logic (which assembles data frames) marks each frame with an ID and schedules it for later, autonomous transmission to the host. The ID allows the host to track and reassemble the data correctly. The frames will be sent to the host at a later time without host intervention, freeing the host from managing the transmission process directly.
14. The SDIO system of claim 1 wherein the first SDIO unit further comprises: a first radio with a transmitter and a receiver and the second SDIO unit further comprises: a first radio with a transmitter and a receiver.
The first SDIO unit includes a radio transmitter and receiver, and the second SDIO unit also includes a radio transmitter and receiver. This implies the SDIO units communicate wirelessly, enabling applications where direct wired connection is not feasible.
15. The SDIO system of claim 1 wherein the first arbitration logic and the second arbitration logic are configured to scatter the transmission of data on the single SDIO bus to reduce electromagnetic interference (EMI).
The arbitration logic in the first and second SDIO units is configured to scatter the data transmission over the single SDIO bus. This scattering is done to reduce electromagnetic interference (EMI). By spreading out the transmissions in time, the system minimizes the peak energy emitted, which can help to meet regulatory requirements and prevent interference with other devices.
16. The SDIO system of claim 1 wherein the first SDIO unit is configured to relay SDIO commands received at the first SDIO unit to the second SDIO unit.
The first SDIO unit can forward SDIO commands received from the host to the second SDIO unit. This relaying capability allows the first unit to act as a proxy or intermediary, simplifying the host's interaction with multiple SDIO units.
17. The SDIO system of claim 1 wherein the SDIO interface further comprises: an SDIO clock (SDIO_CLK) port; an SDIO data (SDIO_DAT) port; and an SDIO command (SDIO_CMD) port.
The single SDIO interface contains a standard SDIO clock (SDIO_CLK) port, SDIO data (SDIO_DAT) port, and SDIO command (SDIO_CMD) port. These ports provide the physical connections for the host to communicate with the SDIO units.
18. The SDIO system of claim 17 wherein the host is configured to broadcast the command address simultaneously to the first SDIO unit and the second SDIO unit via a command line connected to the SDIO_CMD port.
The host broadcasts the command address to the first and second SDIO units simultaneously via a command line connected to the SDIO_CMD port. This allows the host to address both units at the same time using a shared command line.
19. The SDIO system of claim 15 wherein a bus connected to the SDIO data port is a unidirectional data bus driven by the first SDIO unit or the second SDIO unit.
A bus connected to the SDIO data port is a unidirectional data bus driven by the first SDIO unit or the second SDIO unit. The data bus only allows the SDIO units to send data to the host (not the other way around).
20. A secure digital input/output (SDIO) system comprising: a single SDIO interface adapted to be coupled to a host; a single SDIO bus coupled to the SDIO interface; a first SDIO unit coupled to the SDIO bus, the first SDIO unit having a first address and a first relay port; and a second SDIO unit coupled to the SDIO bus and to the first SDIO unit via the first relay port, the second SDIO unit having a second address, and wherein the first SDIO unit is configured to receive a multiple SDIO (MSDIO) command from the host, relay the MSDIO command to the second SDIO device via the first relay port, respond to the MSDIO command via the SDIO bus if the MSDIO command comprises the first address, and wherein the second SDIO unit is configured to receive the MSDIO command from the first SDIO unit, and respond to the MSDIO command via the SDIO bus if the MSDIO command contains the second address.
A system with two SDIO units connected to a single SDIO interface via a single SDIO bus. The first SDIO unit has an address and a relay port, and the second has an address and connects to the first unit via the relay port. The first SDIO unit receives an MSDIO command, relays it to the second. If the command contains the first SDIO unit's address, the first unit responds; if it contains the second unit's address, the second unit responds after receiving the relayed command.
Unknown
November 28, 2017
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