Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A device verification system comprising: a device under test (DUT) including digital logic and a plurality of digital memories coupled to the digital logic; a plurality of hardware Verification Intellectual Property (VIP) modules coupled to the DUT to verify hardware of the DUT; and a plurality of software VIP modules coupled to the DUT to verify firmware of the DUT, wherein the software VIP modules are implemented as Firmware Universal Verification Components (UVCs) that are compliant with Universal Verification Methodology (UVM), where the software VIP modules that are implemented as Firmware UVCs are instantiated and used in a UVM environment like a traditional UVC, where each UVC includes a Master Agent, an Interface coupled to the Master Agent, and a Master Sequence Library, and wherein the Master Agent includes a Sequencer receiving packets from the Master Sequence Library, a Driver receiving packets from the Sequencer, a Config Block and a Monitor, whereby each Firmware UVC provides subroutines to create random sequences of firmware instructions, checks the validity of those instruction sequences, and then measures their coverage in simulation.
A system for testing a device (DUT) includes the DUT itself, which contains digital logic (like a processor) and multiple digital memories. Hardware VIP modules are connected to the DUT to verify the hardware. Software VIP modules, designed as Firmware Universal Verification Components (UVCs) compliant with UVM, are also connected to verify the DUT's firmware. These Firmware UVCs are used in a UVM environment like standard UVCs, and each includes a Master Agent, an Interface for communication, and a Master Sequence Library for generating test sequences. The Master Agent has a Sequencer, a Driver, a Config Block, and a Monitor. The Firmware UVCs generate random firmware instruction sequences, check if the sequences are valid, and measure how much of the firmware has been tested during simulation.
2. A device verification system as recited in claim 1 wherein the digital logic comprises a microprocessor.
The device verification system of the previous description includes a DUT where the digital logic component is a microprocessor. This means the system is designed to specifically test the firmware and hardware interactions within a device that relies on a microprocessor for its core functionality.
3. A device verification system as recited in claim 2 wherein the plurality of memories includes a plurality of non-volatile memories.
The device verification system, which includes a microprocessor as the digital logic, utilizes multiple digital memories within the DUT, and these memories specifically include non-volatile memory. Therefore, the system is tailored to test devices where data must be retained even when power is off, such as embedded systems or devices with persistent storage requirements.
4. A device verification system as recited in claim 3 wherein the plurality of non-volatile memories include a Flash memory and a read-only memory (ROM).
Building on the previous description, the non-volatile memories in the DUT's device verification system include Flash memory and read-only memory (ROM). This further clarifies that the system is designed to test devices using common non-volatile memory types found in many embedded systems, allowing testing of firmware storage and boot-up processes.
5. A device verification system as recited in claim 4 wherein the plurality of memories further includes a volatile memory.
In the device verification system described previously, which includes Flash memory and ROM as non-volatile memories, the DUT also contains volatile memory. This combination of volatile and non-volatile memory types allows the system to test a broader range of device functionalities, including temporary data storage and processing that relies on RAM.
6. A device verification system as recited in claim 5 wherein the volatile memory is a random access memory (RAM).
In the verification system that has volatile and non-volatile memory, the volatile memory is random access memory (RAM). This identifies the specific type of volatile memory used in the DUT, meaning the system tests scenarios involving data storage and retrieval from RAM during device operation.
7. A device verification system as recited in claim 6 wherein the hardware VIP modules comprise peripherals of the DUT.
In the device verification system, where the volatile memory is RAM, the hardware VIP modules are peripherals of the DUT. This means the system is also designed to test the interaction between the core logic/memory and the peripheral devices connected to it, ensuring proper communication and functionality of the entire device.
8. A device verification system as recited in claim 7 wherein the plurality of VIP modules include at least one of a I2C VIP module, a SPI VIP module, a JTAG VIP module, and a AHB Master/Slave VIP module.
The device verification system, which tests peripherals of the DUT, includes VIP modules such as I2C, SPI, JTAG, and AHB Master/Slave. This details specific communication protocols and interfaces that the system is capable of testing, ensuring the DUT's compatibility and correct operation with these standard communication methods.
9. A device verification system comprising: a device under test (DUT); an Interface UVC coupled to the DUT; a Test Bench & Handshake component coupled to the DUT and the Interface UVC; a Reference Model component coupled to the DUT and the Interface UVC; a Firmware UVC, compliant with Universal Verification Methodology (UVM), coupled to the Test Bench & Handshake component, the DUT and the Reference Model component, wherein the Firmware UVC includes a Master Agent, an Interface coupled to the Master Agent, and a Master Sequence Library, and wherein the Master Agent includes a Sequencer receiving packets from the Master Sequence Library, a Driver receiving packets from the Sequencer, a Config Block and a Monitor, wherein the Firmware UVC is instantiated and used in a UVM environment like a traditional UVC and provides subroutines to create random sequences of firmware instructions, checks the validity of those instruction sequences, and then measures their coverage in simulation; and a Coverage component coupled to the Firmware UVC.
A system for verifying a device (DUT) includes an Interface UVC connected to the DUT, a Test Bench & Handshake component connected to both the DUT and the Interface UVC, and a Reference Model component also connected to the DUT and Interface UVC. A Firmware UVC, compliant with UVM, is connected to the Test Bench & Handshake component, the DUT, and the Reference Model component. This Firmware UVC includes a Master Agent, an Interface, and a Master Sequence Library. The Master Agent contains a Sequencer, a Driver, a Config Block, and a Monitor. The Firmware UVC, like a standard UVC, generates random firmware instruction sequences, validates them, and measures coverage during simulation. A Coverage component is connected to the Firmware UVC to assess testing completeness.
10. A device notification system as recited in claim 9 wherein the Driver module and the Monitor module receive data via the Master Agent system interface.
In the device verification system, the Driver module and the Monitor module receive data via the Master Agent system interface. This specifies the communication pathway within the Firmware UVC, detailing how the driver receives instructions and how the monitor observes the behavior of the DUT for verification purposes.
11. A method for verifying the functionality of a device under test comprising: a) automatically developing code segments representing a series of firmware test patterns with a software Verification Intellectual Property (VIP) module, wherein the software VIP module is implemented as a Firmware Universal Verification Component (UVC) that is compliant with Universal Verification Methodology (UVM), where the software VIP modules that are implemented as Firmware UVCs are instantiated and used in a UVM environment like a traditional UVC, where each UVC includes a Master Agent, an Interface coupled to the Master Agent, and a Master Sequence Library, and wherein the Master Agent includes a Sequencer receiving packets from the Master Sequence Library, a Driver receiving packets from the Sequencer, a Config Block and a Monitor, whereby the Firmware UVC provides subroutines to create random sequences of firmware instructions, checks the validity of those instruction sequences, and then measures their coverage in simulation; b) transferring code segments representing the series of firmware test patterns into a digital memory of a device under test (DUT) that includes digital logic; and c) monitoring the functional operation of the DUT as it uses the digital logic to execute the code segments representing the series of firmware test patterns stored in digital memory.
A method for verifying a device (DUT) involves: (a) Automatically generating firmware test patterns using a software Verification Intellectual Property (VIP) module, specifically a Firmware Universal Verification Component (UVC) compliant with UVM. The Firmware UVC is used in a UVM environment like a traditional UVC and includes a Master Agent, Interface, and Master Sequence Library. The Master Agent has a Sequencer, Driver, Config Block, and Monitor. The Firmware UVC provides subroutines to create random sequences of firmware instructions, checks their validity, and measures coverage during simulation. (b) Transferring these test patterns into the DUT's digital memory, which includes digital logic. (c) Monitoring the DUT's operation as it executes the test patterns stored in memory.
12. A method for verifying the functionality of a device under test as recited in claim 11 wherein the UVM is reactive and/or adaptive, such that the test patterns are changed dynamically based upon DUT response.
The firmware verification method described previously, utilizing a UVM-compliant Firmware UVC to generate and execute firmware test patterns, is reactive and/or adaptive. This means the test patterns are changed dynamically based on the DUT's response during the test, allowing for more efficient and targeted testing by focusing on areas where the DUT exhibits unexpected or incorrect behavior.
Unknown
December 5, 2017
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.