9842038

Method and System for Advanced Fail Data Transfer Mechanisms

PublishedDecember 12, 2017
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
20 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method of testing a device under test (DUT), said method comprising: assigning a buffer to each of a plurality of DUTs being tested; testing said plurality of DUTs and receiving fail data therefrom into said buffers; generating an interrupt responsive to a buffer size threshold of a respective buffer being met by a DUT during said testing; responsive to said interrupt and provided said buffer size threshold is low: provided a fail data processing module is idle, assigning a subsequent buffer to said DUT for receiving said fail data and adding said respective buffer to a work list of said fail data processing module; responsive to said interrupt and provided said buffer size threshold is low and said fail data processing module is busy, adjusting said buffer size threshold to a high value; responsive to said interrupt and provided said buffer size threshold is high and an idle list of available buffers comprises at least one available buffer, assigning an available buffer to said DUT for receiving said fail data; and responsive to said interrupt and provided said buffer size threshold is high and said idle list is empty, halting receipt of said fail data for said plurality of DUTs until said idle list comprises at least one available buffer.

2

2. The method as described in claim 1 , wherein said assigning a subsequent buffer further comprises terminating receipt of said fail data in said respective buffer upon said buffer size threshold being met by said DUT.

3

3. The method as described in claim 1 , wherein said adding said respective buffer to a work list further comprises sending control signals to said fail data processing module to process buffers from said work list.

4

4. The method as described in claim 1 , wherein said generating an interrupt further comprises monitoring said fail data processing module to determine whether said fail data processing module is idle or busy responsive to said interrupt.

5

5. The method as described in claim 1 , further comprising removing said respective buffer from said work list upon said fail data processing module completing processing of said fail data stored in said respective buffer.

6

6. The method as described in claim 5 , wherein said removing further comprises adding said respective buffer to said idle list upon said fail data processing module completing processing of said fail data stored in said respective buffer.

7

7. The method as described in claim 1 , wherein said high value is set approximately equal to a maximum buffer capacity level.

8

8. A system for testing a device under test (DUT), said system comprising: a testing engine operable to test a plurality of DUTs and store fail data received therefrom into a plurality of buffers corresponding to said plurality of DUTs, wherein said testing engine is operable to generate an interrupt responsive to a buffer size threshold of a respective buffer being met by a DUT during said test; a fail data processing module operable to process fail data received from said plurality of DUTs; a buffer assigning module operable to assign said plurality of buffers to each of said plurality of DUTs being tested, wherein said buffer assigning module is further operable to: responsive to said interrupt and provided said buffer size threshold is low provided a fail data processing module is idle, assign a subsequent buffer to said DUT for receiving said fail data and add said respective buffer to a work list of said fail data processing module; responsive to said interrupt and provided said buffer size threshold is low and said fail data processing module is busy, adjust said buffer size threshold to a high value; responsive to said interrupt and provided said buffer size threshold is high and an idle list of available buffers comprises at least one available buffer, assign an available buffer to said DUT for receiving said fail data; and responsive to said interrupt and provided said buffer size threshold is high and said idle list is empty, halting receipt of said fail data for said plurality of DUTs until said idle list comprises at least one available buffer.

9

9. The system as described in claim 8 , wherein said buffer assigning module is further operable to terminate receipt of said fail data in said respective buffer upon said buffer size threshold being met by said DUT.

10

10. The system as described in claim 8 , wherein said buffer assigning module is further operable to send control signals to said fail data processing module to process buffers from said work list.

11

11. The system as described in claim 8 , wherein said buffer assigning module is further operable to monitor said fail data processing module to determine whether said fail data processing module is idle or busy responsive to said interrupt.

12

12. The system as described in claim 8 , wherein said buffer assigning module is further operable to remove said respective buffer from said work list upon said fail data processing module completing processing of said fail data stored in said respective buffer.

13

13. The system as described in claim 12 , wherein said buffer assigning module is further operable to add said respective buffer to said idle list upon said fail data processing module completing processing of said fail data stored in said respective buffer.

14

14. The system as described in claim 8 , wherein said high value is set approximately equal to a maximum buffer capacity level.

15

15. A method of testing a device under test (DUT), said method comprising: assigning a buffer to each of a plurality of DUTs being tested; testing said plurality of DUTs and receiving fail data therefrom into said buffers; generating an interrupt responsive to a buffer size threshold of a respective buffer being met by a DUT during said testing; and responsive to said interrupt: monitoring a fail data processor activity level; monitoring an idle list of available buffers and a work list of said fail data processor; assigning a subsequent buffer to said DUT for receiving said fail data based on said idle list, said work list, said buffer size threshold and said fail data processor activity level; and adjusting said buffer size threshold level to a different level for said respective buffer based on said buffer size threshold level being met and said fail data processor activity level.

16

16. The method as described in claim 15 , wherein said assigning a subsequent buffer further comprises assigning said subsequent buffer to said DUT provided said fail data processor activity level is idle and said buffer size threshold is low.

17

17. The method as described in claim 16 , wherein said assigning a subsequent buffer further comprises adding said respective buffer to said work list of said fail data processor.

18

18. The method as described in claim 15 , wherein said adjusting said buffer size threshold level further comprises adjusting said buffer size threshold to a high value provided said buffer size threshold is low and said fail data processor activity level is busy.

19

19. The method as described in claim 18 , wherein said high value is set approximately equal to a maximum buffer capacity level.

20

20. The method as described in claim 15 , further comprising assigning an available buffer to said DUT for receiving said fail data provided said buffer size threshold is high and said idle list comprises at least one available buffer.

Patent Metadata

Filing Date

Unknown

Publication Date

December 12, 2017

Inventors

Xinguo ZHANG
Yi LIU
Ze'ev RAZ
Darrin ALBERS
Alan S. KRECH JR.
Shigeo CHIYODA
Jesse HOBBS

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Cite as: Patentable. “METHOD AND SYSTEM FOR ADVANCED FAIL DATA TRANSFER MECHANISMS” (9842038). https://patentable.app/patents/9842038

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