Simultaneous Multi-Processor Apparatus Applicable to Acheiving Exascale Performance for Algorithms and Program Systems

1. A third apparatus, comprising: a Landing Module (LM) including A) a local clock cycle with a local clock period of at most 2 nanoseconds (ns); B) at least three link interfaces, each adapted to communicate with a distinct link bundle simultaneously sending and/or receiving each of Nchannels of data payloads sufficient to transfer at least 64 bits per local clock cycle of said Nchannels of data channels, where said Nchannels is at least 8; C) each of said link interfaces includes a link input interface and a link output interface, at least one spare link input interface, at least one spare link output interface and a fault recovery circuit; D) said fault recovery circuit is adapted to control said link output interfaces to respond to at least one output channel fault by using a spare channel within said link interface and resending a recent history of an output channel associated with said output channel fault; and E) said fault recovery circuit is adapted to control said link input interfaces to respond to at least one input channel fault by using said spare channel within said link interface to repeat reception of said recent history of an input channel associated with said input channel fault.

2. The third apparatus of claim 1 , further comprising each of said link input interfaces of said link bundle responds to receiving messages as synchronized input messages to said local clock cycle, and further includes a) an error correction and detection pipeline adapted to receive said synchronized input messages and generate error corrected output messages and an error detection signal; b) a message routing pipeline adapted to successively respond to each of said error corrected output messages to generate a routing decision for each of said error corrected output messages.

3. The third apparatus of claim 2 , further comprising each of said link input interfaces further includes a link synchronizer adapted to receive said messages and generate said synchronized input messages to said local clock cycle in response to receiving said messages.

4. The third apparatus of claim 2 , further comprising each of said link output interfaces of said link bundle includes a) a message fault generator adapted to respond to at least one of said error detection signal of said link interface for transmission from said link interface by asserting an output channel fault; and b) an output message prioritizer configured to respond to each of said routing decisions of said error corrected messages of each of said link input interfaces to perform 1) generating an output message for transmission by said link interface, and/or 2) queuing said output message in a link output queue for resend if reception of said output message fails at its incoming message processor.

5. The third apparatus of claim 4 , further comprising at least one of said output message prioritizer is further configured to respond to each of said routing decisions of said error corrected messages of each of said link input interfaces to further perform queuing a second of said output message for later transmission if reception of said second of said output message fails at its said incoming message processor.

6. The third apparatus claim 4 , further comprising a chip including at least one of said LM.

7. The third apparatus of claim 6 , further comprising a module stack and/or a node stack including at least one of said chip.

8. The third apparatus of claim 1 , wherein at least one of said link bundles includes at least one optical fiber to physically transport said data payload.

9. The third apparatus of claim 8 , wherein said optical fiber is adapted to transport said data payload with a bandwidth of Nbits per second; wherein said Nbits is at least 10 billion bits.

10. The third apparatus of claim 9 , wherein said NBits is at least 100 billion bits.

11. The third apparatus of claim 8 , wherein at least one of said link interfaces includes a transceiver adapted to transport said data payload onto and/or off of said optical fiber.

12. The third apparatus of claim 8 , wherein each of said link bundles includes at least one of said optical fiber to physically transport one of said data payload.

13. The third apparatus of claim 12 , wherein said each of said link interfaces includes at least two of said optical fiber to physically transport said one of said data payload.