Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A third apparatus, comprising: a Landing Module (LM) including A) a local clock cycle with a local clock period of at most 2 nanoseconds (ns); B) at least three link interfaces, each adapted to communicate with a distinct link bundle simultaneously sending and/or receiving each of Nchannels of data payloads sufficient to transfer at least 64 bits per local clock cycle of said Nchannels of data channels, where said Nchannels is at least 8; C) each of said link interfaces includes a link input interface and a link output interface, at least one spare link input interface, at least one spare link output interface and a fault recovery circuit; D) said fault recovery circuit is adapted to control said link output interfaces to respond to at least one output channel fault by using a spare channel within said link interface and resending a recent history of an output channel associated with said output channel fault; and E) said fault recovery circuit is adapted to control said link input interfaces to respond to at least one input channel fault by using said spare channel within said link interface to repeat reception of said recent history of an input channel associated with said input channel fault.
A "Landing Module" (LM) for exascale computing has a fast local clock (period of 2 nanoseconds or less). It features at least three link interfaces for simultaneous data transfer. Each interface sends/receives at least 64 bits per clock cycle across at least 8 data channels. Each link interface includes input and output, plus spare input/output channels. A fault recovery circuit automatically handles output channel failures by switching to a spare channel and resending recent data. Similarly, it handles input channel failures by using a spare channel to re-receive recent data, ensuring continuous high-speed communication even with channel faults.
2. The third apparatus of claim 1 , further comprising each of said link input interfaces of said link bundle responds to receiving messages as synchronized input messages to said local clock cycle, and further includes a) an error correction and detection pipeline adapted to receive said synchronized input messages and generate error corrected output messages and an error detection signal; b) a message routing pipeline adapted to successively respond to each of said error corrected output messages to generate a routing decision for each of said error corrected output messages.
Building upon the Landing Module (LM) design which uses multiple link interfaces for data transfer, each link input interface synchronizes incoming messages to the LM's local clock. It includes an error correction and detection pipeline that receives the synchronized messages, corrects errors, and signals any detected errors. A message routing pipeline then determines the destination for each error-corrected message, enabling efficient data distribution within the exascale computing system. This ensures reliable and directed communication.
3. The third apparatus of claim 2 , further comprising each of said link input interfaces further includes a link synchronizer adapted to receive said messages and generate said synchronized input messages to said local clock cycle in response to receiving said messages.
Expanding on the Landing Module (LM) design with error correction and message routing, each link input interface incorporates a link synchronizer. This synchronizer receives incoming messages and aligns them with the LM's local clock cycle, creating synchronized input messages for processing. This synchronization step is crucial for consistent and accurate data handling within the high-speed, parallel processing environment.
4. The third apparatus of claim 2 , further comprising each of said link output interfaces of said link bundle includes a) a message fault generator adapted to respond to at least one of said error detection signal of said link interface for transmission from said link interface by asserting an output channel fault; and b) an output message prioritizer configured to respond to each of said routing decisions of said error corrected messages of each of said link input interfaces to perform 1) generating an output message for transmission by said link interface, and/or 2) queuing said output message in a link output queue for resend if reception of said output message fails at its incoming message processor.
Further developing the Landing Module (LM), each link output interface includes a message fault generator that detects errors based on the error detection signal from the link input. It signals a fault on the output channel if errors are detected. An output message prioritizer decides which message to send next. It either transmits a message directly or queues it for later retransmission if the receiving end reports a failure. This ensures reliable message delivery even in the presence of errors.
5. The third apparatus of claim 4 , further comprising at least one of said output message prioritizer is further configured to respond to each of said routing decisions of said error corrected messages of each of said link input interfaces to further perform queuing a second of said output message for later transmission if reception of said second of said output message fails at its said incoming message processor.
The output message prioritizer described for the Landing Module (LM) includes a feature where, upon a failure notification from a receiving processor, it queues a *second* output message for later transmission. This ensures that if the original message fails, a subsequent message is also held back for retransmission, helping maintain data integrity and reliability across the high-speed communication links. This is in addition to the originally failed message being re-sent.
6. The third apparatus claim 4 , further comprising a chip including at least one of said LM.
The Landing Module (LM), designed for high-speed data transfer and fault tolerance, is implemented as a chip. This means the LM's functions, including fast clock, multiple link interfaces, error correction, and fault recovery, are all integrated onto a single physical chip.
7. The third apparatus of claim 6 , further comprising a module stack and/or a node stack including at least one of said chip.
This chip containing the Landing Module (LM) is incorporated into a module stack or a node stack. This suggests a hierarchical arrangement where multiple LMs or other processing elements are stacked together to create larger processing units, which are then further stacked to form a complete exascale computing system.
8. The third apparatus of claim 1 , wherein at least one of said link bundles includes at least one optical fiber to physically transport said data payload.
The link bundles of the Landing Module (LM), used for high-speed data transfer, utilize optical fibers to physically transmit the data. This indicates a move towards optical communication for improved bandwidth and reduced signal degradation compared to traditional electrical connections.
9. The third apparatus of claim 8 , wherein said optical fiber is adapted to transport said data payload with a bandwidth of Nbits per second; wherein said Nbits is at least 10 billion bits.
The optical fibers used in the Landing Module (LM) link bundles have a bandwidth of at least 10 billion bits per second (10 Gbps). This confirms the system's emphasis on high-speed data transfer using optical communication technology.
10. The third apparatus of claim 9 , wherein said NBits is at least 100 billion bits.
The optical fibers used in the Landing Module (LM) link bundles are further enhanced to have a bandwidth of at least 100 billion bits per second (100 Gbps). This significant increase in bandwidth highlights the extreme performance demands of the exascale computing system.
11. The third apparatus of claim 8 , wherein at least one of said link interfaces includes a transceiver adapted to transport said data payload onto and/or off of said optical fiber.
Each link interface of the Landing Module (LM) which uses optical fibers, includes a transceiver. This transceiver is responsible for converting electrical signals to optical signals for transmission over the fiber, and converting optical signals back to electrical signals upon reception. This is necessary to interface the electronic components of the LM with the optical communication channel.
12. The third apparatus of claim 8 , wherein each of said link bundles includes at least one of said optical fiber to physically transport one of said data payload.
Each link bundle in the Landing Module (LM) uses at least one optical fiber for data transmission. This means that each bundle of communication channels relies on optical technology for at least one of its channels.
13. The third apparatus of claim 12 , wherein said each of said link interfaces includes at least two of said optical fiber to physically transport said one of said data payload.
Each link interface in the Landing Module (LM) has at least *two* optical fibers to transmit a single data payload. This redundancy or parallel transmission could be for increased bandwidth, improved reliability, or a combination of both, by allowing for multiple pathways for the same data.
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December 19, 2017
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