Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An apparatus, comprising: a plurality of registers configured to store information used in execution of a Fast Fourier Transform (FFT) algorithm; and circuitry coupled to the plurality of registers, wherein the circuitry is configured to: set a count value to an initial value; and iteratively process each stage of a plurality of stages included in the FFT algorithm; wherein to process a particular stage of the plurality of stages, the circuitry is further configured to: combine a first portion of the count value and a second portion of the count value to generate a first output value; combine the first output value and an increment value to generate a second output value, wherein the first output value and the second output value correspond to addresses used to access memory locations in a pattern according to execution of the FFT algorithm; increment the count value by the increment value to generate a next count value; and wherein the circuitry is further configured to, in response to a determination that a given stage of the plurality of stages has completed: re-set the count value to the initial value; and modify the increment value.
An apparatus for performing Fast Fourier Transforms (FFTs) includes registers to hold data needed for the FFT algorithm, and circuitry connected to those registers. The circuitry sets a counter to a starting value and then iterates through each stage of the FFT. For each stage, it splits the counter value into two parts, combines these parts to create a first output value (an address), and then combines that address with an increment value to get a second output value (another address). These addresses are used to access memory locations in a pattern required by the FFT. The counter is incremented by the increment value. When a stage is done, the counter resets, and the increment value is updated.
2. The apparatus of claim 1 , wherein the increment value is stored in a particular register of the plurality of registers.
In the FFT apparatus described previously, the increment value (used to calculate memory addresses) is stored in a specific register within the set of registers. This allows the increment value to be easily accessed and modified by the FFT circuitry.
3. The apparatus of claim 2 , wherein to modify the increment value, the circuitry is further configured to perform a shift left operation in the particular register of the plurality of registers.
In the FFT apparatus where the increment value is stored in a register, the circuitry updates this increment value by performing a left bit shift operation on the value within that register. This shift left operation effectively multiplies the increment value by two, changing the memory access pattern for the next FFT stage.
4. The apparatus of claim 1 , wherein the circuitry is further configured to compare a bit at a first position of the count value to a bit at a second position of the next count value, wherein the first position is the same as the second position.
The FFT apparatus compares a bit at a specific position in the current counter value with the bit at the same position in the *next* counter value (after the increment). This comparison helps determine when to modify the increment value or reset the counter.
5. The apparatus of claim 4 , wherein the circuitry includes a counter circuit, and wherein to compare the bit at the first position of the count value to the bit at the second position of the next count value, the circuitry is further configured to perform an exclusive OR operation on the bit at the first position of a current value of the counter circuit and the bit at the second position of a next value of the counter circuit.
In the FFT apparatus that compares bits in the current and next counter values, a counter circuit is used, and the bit comparison is done with an exclusive OR (XOR) operation. The XOR is performed on the bit at the same position in both the current and next values of the counter circuit.
6. The apparatus of claim 1 , wherein the second output value is dependent upon the first output value.
In the FFT apparatus, the second output value (the second memory address) is calculated based on the first output value (the first memory address). This means the two addresses are not independent and are derived sequentially to form the memory access pattern.
7. A method, comprising: setting a count value of a counter circuit to an initial value; iteratively process each stage of a plurality of stages included in a Fast Fourier Transform (FFT) algorithm; wherein processing a particular stage of the plurality of stages includes: combining a first portion of the count value of the counter circuit and a second portion of the count value of the counter circuit to generate a first output value; combining the first output value and an increment value to generate a second output value; wherein the first output value and the second output value correspond to addresses used to access memory locations in a pattern according to execution of the FFT algorithm; incrementing the count value of the counter circuit by the increment value to generate a next count value; and in response to determining a given stage of the plurality of stages has completed: re-setting the count value to the initial value; and modifying the increment value.
A method for performing FFTs involves setting a counter to an initial value and then iterating through each stage of the FFT algorithm. In each stage, the method splits the counter's value into two parts and combines them to generate a first address. It then combines that address with an increment value to generate a second address. These addresses are used to access memory in the correct pattern for the FFT. The counter is incremented by the increment value. When a stage completes, the counter is reset to the initial value, and the increment value is modified.
8. The method of claim 7 , wherein modifying the increment value includes initiating a shift lift operation in a register storing the increment value.
In the FFT method, modifying the increment value involves performing a left bit shift operation on the register that stores the increment value. This effectively doubles the increment, altering the memory access pattern for the subsequent stage.
9. The method of claim 7 , further comprising comparing a first bit of the count value of the counter circuit to a second bit at of the next count value of the counter circuit, the first bit and the second bit occupy a same bit position the count value of the counter circuit and next count value of the counter circuit, respectively.
The FFT method further includes comparing a specific bit within the current counter value to the bit at the same position in the next counter value (after incrementing). This comparison helps determine when to modify the increment or reset the counter.
10. The method of claim 9 , wherein comparing the first bit and the second bit includes performing an exclusive OR operation on the first bit and the second bit.
In the FFT method, the comparison of the bit in the current and next counter values is achieved by performing an exclusive OR (XOR) operation on these two bits.
11. The method of claim 9 , wherein the second output value is dependent upon the first output value.
In the FFT method, the second memory address (second output value) is dependent on the first memory address (first output value). This means that one address is calculated based on the other to achieve the required memory access pattern.
12. The method of claim 11 , wherein combining the first portion of the count value and the second portion of the count value includes combining, using a bitwise OR operation, the first portion of the count value and the second portion of the count value to generate the first output value, and combining the first output value with a particular value stored in a register using a bitwise OR operation to generate the second output value, wherein the particular value is based upon the increment value.
In the FFT method where the second memory address depends on the first, the combination of the two parts of the counter involves a bitwise OR operation. The two parts of the counter are combined using OR to generate the first address. This address is then combined using a bitwise OR operation with a value stored in a register, which is derived from the increment value, to produce the second address.
13. A system, comprising: a processor; a first memory; and a signal processing unit including at least one memory and an address generator circuit, wherein the address generator circuit is configured to: process each stage of a plurality of stages included in a Fast Fourier Transform (FFT) operation; set a count value to an initial value; wherein to process a particular stage of the plurality of stages, the signal processing unit is further configured to: combine a first portion of the count value and a second portion of the count value to generate a first output value; combine the first output value and an increment value to generate a second output value, wherein the first output value and the second output value correspond to addresses used to access memory locations in a pattern according to execution of the FFT operation; increment the count value by the increment value to generate a next count value; and wherein the signal processing unit is further configured to, in response to a determination that a give stage of the plurality of stages has completed: re-set the count value to the initial value; and modify the increment value.
A system for signal processing includes a processor, a first memory, and a signal processing unit with its own memory and an address generator. The address generator runs FFT operations by setting a counter to an initial value and processing each stage. To process a stage, it splits the counter into two parts, combines them to produce a first address, combines that address with an increment to produce a second address. These addresses access memory locations in an FFT-specific pattern. The counter is incremented by the increment value. When a stage completes, the counter is reset, and the increment value is modified.
14. The system of claim 13 , wherein the signal processing unit further includes a plurality of register circuits, wherein the increment value is stored in a particular register circuit of the plurality of register circuits.
In the described signal processing system, the signal processing unit contains registers, and the increment value (used for address generation) is stored in one of those registers.
15. The system of claim 14 , wherein to modify the increment value, the address generator circuit is further configured to perform a shift left operation in the particular register circuit of the plurality of register circuits.
In the signal processing system, the address generator modifies the increment value by performing a left bit shift operation on the register that holds the increment value. This shift left effectively multiplies the increment value by two, changing the memory access pattern for the next FFT stage.
16. The system of claim 15 , wherein address generator circuit is further configured to compare a first bit of the count value to a second bit at of the next count value, wherein the first bit and the second bit occupy a same bit position in the count value and next count value, respectively.
The address generator in the signal processing system compares a bit in the current counter value to the bit at the same position in the next counter value (after incrementing). This bit comparison aids in determining when to modify the increment or reset the counter.
17. The system of claim 16 , wherein to compare the first bit and the second bit, the address generator circuit is further configured to perform an exclusive OR operation on the first bit and the second bit.
In the signal processing system, the comparison of the bits is done using an exclusive OR (XOR) operation on the bit from the current counter value and the corresponding bit from the next counter value.
18. The system of claim 17 , wherein to combine the first portion of the count value and the second portion of the count value, the address generator circuit is further configured to combine, using a bitwise OR operation, the first portion of the count value and the second portion of the count value to generate the first output value, and wherein to combine the first output value with the increment value, the address generator circuit is further configured to perform a bitwise OR operation using the first output value and the increment value to generate the second output value.
In the signal processing system, to generate the first memory address, the address generator combines the two parts of the counter using a bitwise OR operation. The first address is then combined with the increment value, also using a bitwise OR operation, to produce the second memory address.
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December 19, 2017
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