Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor device including a modulator for phase shift keying (PSK) communication, comprising: a reference clock generator configured to generate a reference clock signal; a phase locked loop (PLL) configured to receive the reference clock signal and generate a first clock signal having a frequency different from a frequency of the reference clock signal; an integer divider circuit configured to generate a second clock signal by delaying a rising edge of the reference clock signal by a product of (a) a predetermined integer value included in transmission data and (b) a phase interval; and a processing unit configured to generate a first transmission signal, wherein the first transmission signal is phase-shifted from a first rising edge of the second clock signal, wherein the phase interval is dependent on a ratio of the frequency of the first clock signal to the frequency of the reference clock signal.
A modulator for PSK (Phase Shift Keying) communication uses a semiconductor device with a reference clock generator creating a stable reference clock signal. A PLL (Phase Locked Loop) takes this signal and generates a first clock signal at a different frequency. An integer divider circuit delays the rising edge of the reference clock signal by a specific amount to create a second clock signal. The delay is determined by multiplying a data-dependent integer value with a "phase interval." The core idea is that a processing unit transmits a signal that is phase-shifted relative to the rising edge of this second clock signal. The "phase interval" is calculated based on the ratio between the first and reference clock signal frequencies.
2. The semiconductor device of claim 1 , wherein the ratio of the frequency of the first clock signal to the frequency of the reference clock signal is M, the phase interval is determined by 360° divided by M, and M is non-zero.
In the PSK modulator semiconductor device, the ratio (M) between the first clock frequency (output of PLL) and the reference clock frequency is used to define the phase interval. Specifically, the phase interval is calculated as 360 degrees divided by M, where M is a non-zero value. This ensures that the phase shift applied to the transmission signal is precisely controlled based on the frequency relationship between the two clock signals, allowing for accurate PSK modulation.
3. The semiconductor device of claim 1 , further comprising a pulse generator circuit configured to receive the reference clock signal and generate a reset reference clock signal, wherein: the integer divider circuit is configured to receive the reset reference clock signal from the pulse generator circuit to generate a third clock signal, and the processing unit is configured to generate a second transmission signal, wherein the second transmission signal is phase-shifted from a first rising edge of the third clock signal.
The PSK modulator semiconductor device described in Claim 1 adds a pulse generator that receives the reference clock and creates a "reset reference clock signal". The integer divider uses *this* reset reference clock signal (instead of the original) to generate a *third* clock signal. Now the processing unit uses *this* third clock signal to produce a *second* transmission signal. This second transmission signal is phase-shifted from the rising edge of the third clock signal. Effectively, it introduces a reset mechanism for the timing of the phase shifts.
4. The semiconductor device of claim 3 , wherein the integer divider circuit is configured to generate the third clock signal by delaying a rising edge of the reset reference clock signal by a product of the integer value and the phase interval.
Expanding on Claim 3's design, the integer divider circuit generates the third clock signal (used for the second transmission signal) by delaying the rising edge of the reset reference clock signal. The delay is calculated the same way: as the product of the data-dependent integer value and the phase interval. This ensures the same precise phase shifting mechanism is applied, but now synchronized to the reset reference clock instead of the original reference clock.
5. The semiconductor device of claim 3 , wherein the pulse generator circuit is configured to generate the reset reference clock signal according to a predetermined period.
In the context of the PSK modulator's pulse generator (Claim 3), the reset reference clock signal is not arbitrary; it is generated according to a defined period. This means the pulse generator outputs pulses at regular time intervals, creating a consistent timing signal for resetting the phase shift calculation in the integer divider circuit and ensuring periodic synchronization of the transmission signal.
6. The semiconductor device of claim 3 , wherein: the pulse generator circuit is configured to generate a first reset reference clock signal and a second reset reference clock signal, and the integer divider circuit is configured to generate the third clock signal based on a rising edge of the first reset reference clock signal, and to generate a fourth clock signal based on a rising edge of the second reset reference clock signal.
Building upon Claim 3, instead of a single reset reference clock signal, the pulse generator creates *two*: a first and a second reset reference clock signal. The integer divider then generates the third clock signal (for the second transmission signal) based on the rising edge of the *first* reset signal. It also generates a *fourth* clock signal based on the rising edge of the *second* reset signal. This introduces the possibility of different timing references.
7. The semiconductor device of claim 6 , wherein: the processing unit is configured to generate a third transmission signal, the third transmission signal is phase-shifted from a rising edge of the fourth clock signal, and the third transmission signal is different from the second transmission signal.
Continuing from Claim 6, the processing unit generates a *third* transmission signal. This third transmission signal is phase-shifted from the rising edge of the *fourth* clock signal (derived from the second reset reference clock). Critically, *this* third transmission signal is different from the *second* transmission signal (derived from the first reset reference clock). This allows for two distinct, independently timed, phase-modulated signals from the same device.
8. The semiconductor device of claim 1 , wherein the processing unit is configured to generate the first transmission signal having a value delayed by a width between the first rising edge of the second clock signal and a second rising edge closest to the first rising edge of the second clock signal.
The PSK modulator semiconductor device, as described in Claim 1, controls the phase shift by delaying the *value* (high or low voltage) of the first transmission signal. The delay duration is equal to the time width between a rising edge of the second clock signal and the very next rising edge of the *same* second clock signal. In essence, the transmitted symbol is held for one full cycle of that second clock.
9. The semiconductor device of claim 1 , wherein the semiconductor device comprises a Near Field Communication (NFC) transmitter configured to transmit the first transmission signal.
The PSK modulator semiconductor device detailed in Claim 1 is used as part of a Near Field Communication (NFC) transmitter. The first transmission signal generated by the device is the signal that the NFC transmitter sends wirelessly. The phase modulation allows the NFC transmitter to encode data.
10. A semiconductor device including a modulator for phase shift keying (PSK) communication, comprising: an integer divider circuit configured to receive a first clock signal having a frequency that is a multiple of a frequency of a reference clock signal, to receive a reset reference clock signal, and to generate a second clock signal by delaying a rising edge of the reset reference clock signal by a product of (a) a predetermined integer value included in transmission data and (b) a phase interval; and a processing unit configured to generate a first transmission signal, wherein the first transmission signal is phase-shifted from a first rising edge of the second clock signal, wherein the phase interval is dependent on a ratio of the frequency of the first clock signal to the frequency of the reference clock signal.
A semiconductor device incorporates a modulator for PSK communication. It has an integer divider that receives a first clock signal (frequency is a multiple of a reference clock's frequency) and a reset reference clock signal. The divider generates a second clock signal by delaying the rising edge of the reset reference clock by a product of an integer (from transmission data) and a phase interval. A processing unit generates a first transmission signal, phase-shifted from the rising edge of the second clock signal. The phase interval depends on the frequency ratio between the first clock and the reference clock.
11. The semiconductor device of claim 10 , wherein the ratio of the frequency of the first clock signal to the frequency of the reference clock signal is M, the phase interval is determined by 360° divided by M, and M is non-zero.
In this PSK modulator (Claim 10), the ratio (M) of the first clock signal's frequency to the reference clock signal's frequency determines the phase interval. The interval is 360 degrees divided by M, with M being a non-zero value. This maintains precise phase control based on the frequency relationship between the clock signals.
12. The semiconductor device of claim 10 , wherein: the integer divider circuit is configured to receive a first reset reference clock signal and a second reset reference clock signal, the integer divider circuit is configured to generate the second clock signal based on a rising edge of the first reset reference clock signal, and the integer divider circuit is configured to generate a third clock signal based on a rising edge of the second reset reference clock signal.
Extending Claim 10, the integer divider receives *two* reset reference clock signals: a first and a second. It generates the second clock signal based on the rising edge of the *first* reset signal and generates a *third* clock signal based on the rising edge of the *second* reset signal. This allows for two independent clock signals to be used for PSK modulation.
13. The semiconductor device of claim 12 , wherein: the processing unit is configured to generate a second transmission signal, the second transmission signal is phase-shifted from a rising edge of the third clock signal, and the second transmission signal is different from the first transmission signal.
The PSK modulator (Claim 12) has a processing unit that generates a *second* transmission signal, phase-shifted from the rising edge of the *third* clock signal. This second transmission signal is *different* from the *first* transmission signal, allowing for the generation of two independently modulated signals from the same device.
14. The semiconductor device of claim 10 , wherein the processing unit is configured to generate the first transmission signal having a value delayed by a width between the first rising edge of the second clock signal and a second rising edge closest to the first rising edge of the second clock signal.
The PSK modulator (Claim 10) delays the *value* of the first transmission signal. The delay is the time between a rising edge of the second clock signal and the next rising edge of the *same* second clock signal, ensuring that the transmitted symbol is held for one full cycle of the second clock.
15. The semiconductor device of claim 10 , wherein the semiconductor device comprises a Near Field Communication (NFC) transmitter configured to transmit the first transmission signal.
The PSK modulator (Claim 10) is part of a Near Field Communication (NFC) transmitter. The first transmission signal is what the NFC transmitter sends wirelessly, encoding data through phase modulation.
16. A semiconductor device including a demodulator for phase shift keying (PSK) communication, comprising: a phase detector circuit configured to receive a first clock signal and generate a second clock signal by detecting a phase shift value of the first clock signal; a phase locked loop (PLL) configured to generate a third clock signal having a frequency that is a multiple of a frequency of a reference clock signal; and a counter unit configured to calculate an integer value corresponding to a delayed phase value by comparing the second clock signal with the third clock signal, wherein the demodulator is configured to perform a demodulation dependent on the delayed phase value; wherein the phase detector circuit is configured to cause the second clock signal to have a logic level value corresponding to a width between a first rising edge of the reference clock signal and a first rising edge of the first clock signal, and wherein when a second rising edge of the first clock signal is ahead of a second rising edge of the reference clock signal, the phase detector circuit is configured to cause the second clock signal to have a logic level value corresponding to a width between the second rising edge of the reference clock signal and a third rising edge closest to and after the second rising edge of the first clock signal.
A semiconductor device incorporates a demodulator for PSK communication. A phase detector circuit takes a first clock signal and creates a second clock signal by detecting its phase shift. A PLL generates a third clock signal whose frequency is a multiple of a reference clock's frequency. A counter unit calculates an integer value corresponding to the delayed phase by comparing the second clock signal to the third clock signal. The demodulation process depends on this delayed phase value. The phase detector makes the second clock have a logic level (high or low) matching the time difference between the first rising edges of the reference and first clock signals. If the first clock signal's rising edge is ahead of the reference clock, the logic level matches the time between the *second* rising edge of the reference clock and the *third* rising edge of the first clock (the one after the second).
17. The semiconductor device of claim 16 , wherein a ratio of the frequency of the third clock signal to the frequency of the reference clock signal is M, a phase interval is determined by 360° divided by M, and M is non-zero.
The PSK demodulator (Claim 16) has a ratio (M) between the third clock frequency and the reference clock frequency. A phase interval is calculated as 360 degrees divided by M, with M being a non-zero value. This ensures a precise phase interval is used for demodulation calculations.
18. The semiconductor device of claim 17 , wherein the counter unit is configured to calculate the integer value as a ratio of the phase shift value to the phase interval.
In the PSK demodulator (Claim 17), the counter unit calculates the integer value by dividing the phase shift value by the phase interval. This allows the demodulator to determine the original data value encoded in the phase shift.
19. The semiconductor device of claim 16 , wherein the logic level value is a high level logical value.
In the PSK demodulator (Claim 16), the logic level of the second clock signal, which represents the phase difference, is a *high* logic level. This specifies how the phase information is encoded within the signal for processing.
20. The semiconductor device of claim 16 , wherein the semiconductor device comprises a Near Field Communication (NFC) receiver configured to receive the first clock signal.
The PSK demodulator (Claim 16) is part of a Near Field Communication (NFC) receiver. The first clock signal, which contains the phase-modulated data, is received by the NFC receiver.
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December 19, 2017
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