Semiconductor Device and Communication System Including the Same

1. A semiconductor device including a modulator for phase shift keying (PSK) communication, comprising: a reference clock generator configured to generate a reference clock signal; a phase locked loop (PLL) configured to receive the reference clock signal and generate a first clock signal having a frequency different from a frequency of the reference clock signal; an integer divider circuit configured to generate a second clock signal by delaying a rising edge of the reference clock signal by a product of (a) a predetermined integer value included in transmission data and (b) a phase interval; and a processing unit configured to generate a first transmission signal, wherein the first transmission signal is phase-shifted from a first rising edge of the second clock signal, wherein the phase interval is dependent on a ratio of the frequency of the first clock signal to the frequency of the reference clock signal.

2. The semiconductor device of claim 1 , wherein the ratio of the frequency of the first clock signal to the frequency of the reference clock signal is M, the phase interval is determined by 360° divided by M, and M is non-zero.

3. The semiconductor device of claim 1 , further comprising a pulse generator circuit configured to receive the reference clock signal and generate a reset reference clock signal, wherein: the integer divider circuit is configured to receive the reset reference clock signal from the pulse generator circuit to generate a third clock signal, and the processing unit is configured to generate a second transmission signal, wherein the second transmission signal is phase-shifted from a first rising edge of the third clock signal.

4. The semiconductor device of claim 3 , wherein the integer divider circuit is configured to generate the third clock signal by delaying a rising edge of the reset reference clock signal by a product of the integer value and the phase interval.

5. The semiconductor device of claim 3 , wherein the pulse generator circuit is configured to generate the reset reference clock signal according to a predetermined period.

6. The semiconductor device of claim 3 , wherein: the pulse generator circuit is configured to generate a first reset reference clock signal and a second reset reference clock signal, and the integer divider circuit is configured to generate the third clock signal based on a rising edge of the first reset reference clock signal, and to generate a fourth clock signal based on a rising edge of the second reset reference clock signal.

7. The semiconductor device of claim 6 , wherein: the processing unit is configured to generate a third transmission signal, the third transmission signal is phase-shifted from a rising edge of the fourth clock signal, and the third transmission signal is different from the second transmission signal.

8. The semiconductor device of claim 1 , wherein the processing unit is configured to generate the first transmission signal having a value delayed by a width between the first rising edge of the second clock signal and a second rising edge closest to the first rising edge of the second clock signal.

9. The semiconductor device of claim 1 , wherein the semiconductor device comprises a Near Field Communication (NFC) transmitter configured to transmit the first transmission signal.

10. A semiconductor device including a modulator for phase shift keying (PSK) communication, comprising: an integer divider circuit configured to receive a first clock signal having a frequency that is a multiple of a frequency of a reference clock signal, to receive a reset reference clock signal, and to generate a second clock signal by delaying a rising edge of the reset reference clock signal by a product of (a) a predetermined integer value included in transmission data and (b) a phase interval; and a processing unit configured to generate a first transmission signal, wherein the first transmission signal is phase-shifted from a first rising edge of the second clock signal, wherein the phase interval is dependent on a ratio of the frequency of the first clock signal to the frequency of the reference clock signal.

11. The semiconductor device of claim 10 , wherein the ratio of the frequency of the first clock signal to the frequency of the reference clock signal is M, the phase interval is determined by 360° divided by M, and M is non-zero.

12. The semiconductor device of claim 10 , wherein: the integer divider circuit is configured to receive a first reset reference clock signal and a second reset reference clock signal, the integer divider circuit is configured to generate the second clock signal based on a rising edge of the first reset reference clock signal, and the integer divider circuit is configured to generate a third clock signal based on a rising edge of the second reset reference clock signal.

13. The semiconductor device of claim 12 , wherein: the processing unit is configured to generate a second transmission signal, the second transmission signal is phase-shifted from a rising edge of the third clock signal, and the second transmission signal is different from the first transmission signal.

14. The semiconductor device of claim 10 , wherein the processing unit is configured to generate the first transmission signal having a value delayed by a width between the first rising edge of the second clock signal and a second rising edge closest to the first rising edge of the second clock signal.

15. The semiconductor device of claim 10 , wherein the semiconductor device comprises a Near Field Communication (NFC) transmitter configured to transmit the first transmission signal.

16. A semiconductor device including a demodulator for phase shift keying (PSK) communication, comprising: a phase detector circuit configured to receive a first clock signal and generate a second clock signal by detecting a phase shift value of the first clock signal; a phase locked loop (PLL) configured to generate a third clock signal having a frequency that is a multiple of a frequency of a reference clock signal; and a counter unit configured to calculate an integer value corresponding to a delayed phase value by comparing the second clock signal with the third clock signal, wherein the demodulator is configured to perform a demodulation dependent on the delayed phase value; wherein the phase detector circuit is configured to cause the second clock signal to have a logic level value corresponding to a width between a first rising edge of the reference clock signal and a first rising edge of the first clock signal, and wherein when a second rising edge of the first clock signal is ahead of a second rising edge of the reference clock signal, the phase detector circuit is configured to cause the second clock signal to have a logic level value corresponding to a width between the second rising edge of the reference clock signal and a third rising edge closest to and after the second rising edge of the first clock signal.

17. The semiconductor device of claim 16 , wherein a ratio of the frequency of the third clock signal to the frequency of the reference clock signal is M, a phase interval is determined by 360° divided by M, and M is non-zero.

18. The semiconductor device of claim 17 , wherein the counter unit is configured to calculate the integer value as a ratio of the phase shift value to the phase interval.

19. The semiconductor device of claim 16 , wherein the logic level value is a high level logical value.

20. The semiconductor device of claim 16 , wherein the semiconductor device comprises a Near Field Communication (NFC) receiver configured to receive the first clock signal.