Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A device comprising: a memory array including two transistor, two capacitor (2T-2C) ferroelectric memory cells arranged in rows and columns; and a memory controller configured to: write a data pattern to a set of 2T-2C ferroelectric memory cells in the memory array, wherein the write is performed in a one transistor, one-capacitor (1T-1C) mode; and read the 2T-2C ferroelectric memory cells in a 2T-2C mode after the data pattern is written to generate a random number.
A memory device uses a memory array composed of two-transistor, two-capacitor (2T-2C) ferroelectric memory cells arranged in rows and columns. A memory controller writes a data pattern to a set of these 2T-2C cells using a one-transistor, one-capacitor (1T-1C) mode. After writing, the controller reads the 2T-2C cells in a 2T-2C mode. This read operation generates a random number based on the slight variations in the ferroelectric capacitors.
2. The device of claim 1 , wherein the memory controller is configured to store the random number in the set of 2T-2C ferroelectric memory cells by rewriting the random number to the set of 2T-2C ferroelectric cells after the reading of the set of 2T-2C ferroelectric memory cells, but within the same memory cycle as the reading.
The memory device described in Claim 1 includes a memory controller that stores the generated random number back into the same set of 2T-2C ferroelectric memory cells by rewriting the random number to them immediately after reading. This rewrite process happens within the same memory cycle as the read operation, ensuring that the random number is quickly available for subsequent use.
3. The device of claim 1 , wherein the data pattern is a uniform data pattern that includes all logic 0 values or all logic 1 values.
In the memory device described in Claim 1, the data pattern written to the 2T-2C ferroelectric memory cells before reading is a uniform pattern. This pattern consists of either all logic 0 values or all logic 1 values written to each cell in the selected set.
4. The device of claim 1 , wherein each 2T-2C ferroelectric memory cell comprises a first ferroelectric capacitor, a second ferroelectric capacitor, a first transistor, and a second transistor, wherein the first ferroelectric capacitor is coupled to a first bit line by a source-drain path of the first transistor and the second ferroelectric capacitor is coupled to a second bit line by a source-drain path of the second transistor, wherein the data pattern is a uniform data pattern of a first logic value, and wherein writing the uniform data pattern to the 2T-2C ferroelectric memory cells in the 1T-1C mode comprises: for each of the 2T-2C ferroelectric memory cells, polarizing each of the first and second ferroelectric capacitors to a first polarization state corresponding to the first logic value.
In the memory device described in Claim 1, each 2T-2C cell contains two ferroelectric capacitors and two transistors. The first capacitor connects to a first bit line through the first transistor, and the second capacitor connects to a second bit line through the second transistor. The data pattern written is a uniform pattern (all 0s or all 1s). Writing this uniform pattern in 1T-1C mode means, for each 2T-2C cell, polarizing both the first and second capacitors to the same polarization state, corresponding to the chosen logic value (either 0 or 1).
5. The device of claim 4 , wherein the first and second bit lines of each 2T-2C ferroelectric memory cell are coupled to first and second inputs, respectively, of a sense amplifier, and wherein generating the random number by reading the 2T-2C ferroelectric memory cells in the 2T-2C mode comprises: for each of the 2T-2C ferroelectric memory cells: using the first bit line to provide a first signal corresponding to the first polarization state of the first ferroelectric capacitor to the first input; using the second bit line to provide a second signal corresponding to the first polarization state of the second ferroelectric capacitor to the second input, wherein the first and second signals are not complementary signals; and producing, by the sense amplifier, a data bit having either the first logic value or a second logic value.
The memory device described in Claim 4 has the first and second bit lines of each 2T-2C memory cell connected to the inputs of a sense amplifier. Generating a random number involves reading in 2T-2C mode. For each cell, the first bit line sends a signal representing the first capacitor's polarization state to the first input of the sense amplifier. Similarly, the second bit line sends a signal representing the second capacitor's polarization state to the second input. These signals aren't complementary. The sense amplifier then outputs a data bit (0 or 1) based on the slight differences, effectively generating a random bit.
6. The device of claim 5 , wherein the random number has a number of bits equal to the number of 2T-2C ferroelectric memory cells of the set, and the data bit produced by each 2T-2C ferroelectric memory cell corresponds to a respective bit of the random number.
In the memory device described in Claim 5, the generated random number contains a number of bits equal to the number of 2T-2C ferroelectric memory cells in the selected set. Each 2T-2C cell contributes one random bit to the final random number produced by the sense amplifier.
7. The device of claim 5 , wherein the memory controller is configured to rewrite the random number to the 2T-2C ferroelectric cells by, for each 2T-2C ferroelectric memory cell: polarizing the first ferroelectric capacitor to a polarization state corresponding to the logic value of the data bit; and polarizing the second ferroelectric capacitor to a polarization state corresponding to the complement of the logic value of the data bit.
In the memory device described in Claim 5, after the random number is generated, the memory controller rewrites it to the 2T-2C cells. This rewrite operation involves, for each 2T-2C cell, setting the polarization of the first capacitor to match the logic value of the generated random bit. Simultaneously, the polarization of the second capacitor is set to the complement (opposite) of that logic value.
8. The device of claim 1 , wherein each 2T-2C ferroelectric memory cell comprises a first ferroelectric capacitor, a second ferroelectric capacitor, a first transistor, and a second transistor, wherein the first ferroelectric capacitor is coupled to a first bit line by a source-drain path of the first transistor and the second ferroelectric capacitor is coupled to a second bit line by a source-drain path of the second transistor, wherein the data pattern is a non-uniform data pattern, and wherein writing the non-uniform data pattern to the 2T-2C ferroelectric memory cells in the 1T-1C mode comprises: for each of at least one but not all of the 2T-2C ferroelectric memory cells, polarizing each of the first and second ferroelectric capacitors to a first polarization state corresponding to a first logic value; and for each of the remaining 2T-2C ferroelectric memory cells, polarizing each of the first and second ferroelectric capacitors to a second polarization state corresponding to a second logic value that is the complement of the first logic value.
In the memory device described in Claim 1, each 2T-2C cell comprises two ferroelectric capacitors and two transistors, with each capacitor connected to a bit line through a transistor. The data pattern written is a *non-uniform* pattern. Writing this in 1T-1C mode means that *some* 2T-2C cells have both capacitors polarized to a first logic value (e.g., 0), while the *remaining* 2T-2C cells have both capacitors polarized to the opposite logic value (e.g., 1).
9. A system comprising: a ferroelectric random access memory (FRAM) array comprising a plurality of two transistor, two capacitor (2T-2C) memory cells arranged in rows and columns; a processor configured to generate a random number using a set of 2T-2C memory cells from the FRAM array by: performing a write operation in a one transistor, one-capacitor (1T-1C) mode to write a uniform data pattern to the set of 2T-2C memory cells; after writing the uniform data pattern, performing a read operation in a 2T-2C mode on the set of 2T-2C memory cells to produce the random number.
A system incorporates a ferroelectric random access memory (FRAM) array consisting of 2T-2C memory cells arranged in rows and columns. A processor generates a random number using a selected set of these 2T-2C cells. It writes a uniform data pattern (all 0s or all 1s) to the cells using a 1T-1C write mode. Then, it reads the cells in a 2T-2C mode to produce the random number.
10. The system of claim 9 , wherein the processor is configured to store the random number in the 2T-2C memory cells by a rewrite operation performed in the same cycle as the read operation.
The system described in Claim 9 has a processor that stores the generated random number back into the 2T-2C memory cells by performing a rewrite operation. This rewrite is performed in the same memory cycle as the read operation that generated the random number.
11. The system of claim 9 , wherein each 2T-2C memory cell comprises: a first sub-cell having a first ferroelectric capacitor and a first transistor, the first ferroelectric capacitor being coupled to a first bit line by a source-drain path of the first transistor; and a second sub-cell having a second ferroelectric capacitor and a second transistor, the second ferroelectric capacitor being coupled to a second bit line by a source-drain path of the second transistor; wherein the first and second bit lines are coupled to first and second inputs, respectively, of a sense amplifier.
In the system described in Claim 9, each 2T-2C memory cell has two sub-cells. The first sub-cell includes a ferroelectric capacitor and a transistor, with the capacitor connected to a bit line through the transistor. The second sub-cell mirrors this setup. The two bit lines from each 2T-2C memory cell connect to the two inputs of a sense amplifier.
12. The system of claim 11 , wherein writing the uniform data pattern in the 1T-1C mode comprises, for each of the 2T-2C memory cells, polarizing each of the first and second ferroelectric capacitors to a first polarization state corresponding to a first logic value.
In the system described in Claim 11, writing the uniform data pattern in the 1T-1C mode means, for each 2T-2C memory cell, setting both the first and second ferroelectric capacitors to the same polarization state corresponding to a single logic value (either 0 or 1).
13. The system of claim 12 , wherein reading the 2T-2C memory cells in the 2T-2C mode comprises, for each of the 2T-2C memory cells: providing a first signal corresponding to the polarization state of the first ferroelectric capacitor to the first input of the sense amplifier using the first bit line; providing a second signal corresponding to the polarization state of the second ferroelectric capacitor to the second input of the sense amplifier using the second bit line; and in response to the first and second signals, outputting from the sense amplifier a random data bit having either the first logic value or a second logic value that is the complement of the first logic value; wherein the random data bit corresponds to one bit of the random number.
In the system described in Claim 12, reading the 2T-2C memory cells in the 2T-2C mode involves, for each cell, sending a signal corresponding to the first capacitor's polarization to one input of the sense amplifier and a signal from the second capacitor to the other input. The sense amplifier then outputs a random data bit (either 0 or 1) based on the subtle differences in these signals. Each of these random bits corresponds to a bit in the final random number.
14. The system of claim 9 , wherein the set of 2T-2C memory cells is located in a reserved area of the FRAM array.
In the system described in Claim 9, the set of 2T-2C memory cells used for random number generation is located in a reserved section of the FRAM array.
15. The system of claim 9 , wherein the set of 2T-2C memory cells include memory cells located in different rows of the FRAM array.
In the system described in Claim 9, the selected 2T-2C memory cells used for random number generation are not all in the same row. They are located across different rows of the FRAM array.
16. The system of claim 9 , wherein the system is one of an integrated circuit, a microcontroller unit, an embedded processor, or a system-on-chip.
The system described in Claim 9 is implemented as one of the following: an integrated circuit, a microcontroller unit, an embedded processor, or a system-on-chip.
17. A method for using n two transistor, two capacitor (2T-2C) ferroelectric memory cells to generate an n-bit random number, the method comprising: for each of the n 2T-2C ferroelectric memory cells, where n is an integer greater than or equal to 1: polarizing each of a first ferroelectric capacitor and a second ferroelectric capacitor of the 2T-2C ferroelectric memory cell to a first polarization state corresponding to a first logic value; providing, to a first input of a sense amplifier, a first signal corresponding to the first logic value on a first bit line coupled to the first ferroelectric capacitor; providing, to a second input of the sense amplifier, a second signal corresponding to the first logic value on a second bit line coupled to the second ferroelectric capacitor; and producing, using the sense amplifier, a random data bit having one of the first logic value or a second logic value in response to receiving the first and second signals.
A method to generate an n-bit random number uses n two-transistor, two-capacitor (2T-2C) ferroelectric memory cells. For each cell, both the first and second ferroelectric capacitors are polarized to the same logic value (0 or 1). A signal representing this logic value is then sent from each capacitor to a sense amplifier via their respective bit lines. The sense amplifier outputs a random data bit (0 or 1) in response to receiving these signals, exploiting minor differences in capacitor behavior.
18. The method of claim 17 , wherein the random data bit corresponds to one bit of the n-bit random number.
In the random number generation method described in Claim 17, the generated random data bit from each 2T-2C cell represents one bit of the final n-bit random number.
19. The method of claim 17 , wherein the first logic value corresponds to a “0” data state and the second logic value corresponds to a “1” data state.
In the random number generation method described in Claim 17, the first logic value used to polarize the capacitors corresponds to a "0" data state, and the second logic value generated by the sense amplifier corresponds to a "1" data state.
20. The method of claim 17 , wherein the first logic value corresponds to a “1” data state and the second logic value corresponds to a “0” data state.
In the random number generation method described in Claim 17, the first logic value used to polarize the capacitors corresponds to a "1" data state, and the second logic value generated by the sense amplifier corresponds to a "0" data state.
21. The method of claim 17 , wherein the sense amplifier is a differential sense amplifier and the random data bit is produced in response to the first and second signals not being complementary signals.
In the random number generation method described in Claim 17, the sense amplifier used is a differential sense amplifier. The random data bit is generated because the signals received from the two ferroelectric capacitors are not perfectly complementary (i.e., not exact opposites).
22. The method of claim 17 , comprising: for each of the n 2T-2C ferroelectric memory cells: after producing the random data bit, polarizing the first ferroelectric capacitor to a polarization state corresponding to the logic value of the random data bit; and polarizing the second ferroelectric capacitor to a polarization state corresponding to the complement of the logic value of the random data bit.
The method described in Claim 17 further includes, after a random data bit is generated for each 2T-2C cell, polarizing the first ferroelectric capacitor to a polarization state corresponding to the logic value of that random bit. At the same time, the second ferroelectric capacitor is polarized to the complement of that logic value.
Unknown
December 26, 2017
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.