Memory System and Information Processing System

1. A memory system comprising: a memory; a circuit; and a processor, wherein the memory includes a user data region and a management region, wherein the user data region is divided into a plurality of blocks, wherein the circuit is configured to check and correct an error of data read from a block among the plurality of blocks, wherein the management region stores access information of each of the plurality of blocks as a management table, wherein a value of the access information is either a first value indicating that the number of access times is 0 or a second value indicating that the number of access times is greater than or equal to 1, wherein the processor is configured to determine the value of the access information, to control writing and reading of the management region, to control writing and reading of the user data region, and to control the circuit, and wherein when the value of the access information of the block is the second value, the processor controls the circuit so that the circuit does not check and correct an error of data read from the block.

2. The memory system according to claim 1 , wherein when the circuit checks and corrects an error, the processor controls the circuit so that the value of the access information of the block is the second value.

3. The memory system according to claim 1 , wherein if there is a write access to the user data region, the processor controls the circuit so that the value of the access information of the block is the second value.

4. The memory system according to claim 1 , wherein when power is turned on, the processor controls the circuit so that the management table is initialized to the first value.

5. The memory system according to claim 1 , wherein if there is a block in which the value of the access information is the first value when power is turned off, the processor controls the circuit so that the circuit checks and corrects an error of data read from the block.

6. The memory system according to claim 1 , wherein the memory includes a plurality of memory cells, wherein each of the plurality of memory cells includes a retention node and a transistor capable of controlling charging and discharging of the retention node, and wherein a channel formation region of the transistor is formed using an oxide semiconductor.

7. An information processing system comprising: the memory system according to claim 1 ; and a host device, wherein the host device is connected to the memory system so that the host device can access the user data region.