9852107

Techniques for scalable endpoint addressing for parallel applications

PublishedDecember 26, 2017
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
24 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for performing inter-process communication between nodes of a multi-node system, the method comprising: receiving, by circuitry, a packet from a remote node including a target virtual process identifier and at least one memory operation; translating, by the circuitry, the virtual process identifier into a local process identifier that corresponds with a local process; and causing, by the circuitry, the at least one memory operation to be performed against a region of memory associated with the local process.

2

2. The method of claim 1 , wherein the circuitry comprises a network interface circuit.

3

3. The method of claim 1 , wherein causing the at least one memory operation to be performed against the region of memory associated with the local process further includes the circuitry performing direct memory access (DMA) on a memory device.

4

4. The method of claim 1 , wherein translating the virtual process identifier into the local process identifier that corresponds with the local process further includes the circuitry traversing a map to identify a local process that corresponds with the target virtual process identifier.

5

5. The method of claim 1 , wherein the packet further includes a job tag, the job tag being associated with one or more local processes of a node.

6

6. The method of claim 5 , wherein translating the virtual process identifier into the local process identifier that corresponds with the local process further includes: accessing a content addressable memory (CAM) device to determine a base process address based on the job tag; and calculating the local process identifier by summing the base process address and the target virtual process identifier.

7

7. The method of claim 5 , wherein translating the virtual process identifier into the local process identifier that corresponds with the local process further includes: accessing a content addressable memory (CAM) device to determine a base process address based on the job tag; calculating a process identifier by summing the base process address and the target virtual process identifier; and accessing a process identifier relocation table to locate a local process identifier associated with the calculated process identifier.

8

8. The method of claim 1 , wherein the virtual process identifier is based on an algorithmic mapping that maps a plurality of physical processes across N number of nodes.

9

9. A system comprising: a first node device comprising: a memory; a controller coupled to the memory and configured to execute at least one local process, the at least one local process being associated with a region of the memory and a local process identifier; circuitry communicatively coupled to the controller and configured to be communicatively coupled to a multi-node network, the circuitry being configured to: receive a packet from a remote node via the multi-node network, the packet including a virtual process identifier and at least one memory operation; identify a target local process at least in part by translating the virtual process identifier into a local process identifier that corresponds with the target local process; and cause the at least one memory operation to be performed against a region of memory associated with the target local process.

10

10. The system of claim 9 , wherein the circuitry comprises a network interface circuit.

11

11. The system of claim 9 , wherein causing the at least one memory operation to be performed against the region of memory associated with the target local process further includes the circuitry performing direct memory access (DMA) on the memory.

12

12. The system of claim 9 , wherein translating the virtual process identifier into the local process identifier that corresponds with the local process further includes the circuitry traversing a map to identify a local process that corresponds with the virtual process identifier.

13

13. The system of claim 9 , wherein the packet further includes a job tag, the job tag being associated with one or more local processes of the first node device.

14

14. The system of claim 13 , wherein the first node device further comprises a content addressable memory (CAM) device.

15

15. The system of claim 14 , wherein the circuitry is further configured to: access the CAM device to determine a base process address based on the job tag; and identify the target local process by summing the base process address and the virtual process identifier.

16

16. The system of claim 14 , wherein the circuitry is further configured to: access the CAM device to determine a base process address based on the job tag; and calculate a process identifier by summing the base process address and the virtual process identifier; and identify the target local process by accessing a process identifier relocation table in the memory to locate the local process identifier associated with the calculated process identifier.

17

17. A non-transitory computer-readable medium having a plurality of instructions encoded thereon that when executed by at least one processor cause a process to be carried out, the process comprising: receiving a packet from a remote node via a multi-node network, the packet including a target virtual process identifier and at least one memory operation; translating the virtual process identifier into a local process identifier that corresponds with a local process; and causing the at least one memory operation to be performed against a region of memory associated with the local process.

18

18. The computer-readable medium of claim 17 , wherein the memory operation is a get or set operation.

19

19. The computer-readable medium of claim 17 , wherein causing the at least one memory operation to be performed against a region of memory associated with the local process further includes causing circuitry to perform direct memory access (DMA) on a memory device.

20

20. The computer-readable medium of claim 17 , wherein translating the virtual process identifier into the local process identifier that corresponds with the local process further includes traversing a map to identify a local process that corresponds with the target virtual process identifier.

21

21. A system comprising: a memory; means for receiving a packet from a remote node via a multi-node network, the packet including a virtual process identifier and at least one memory operation; means for identifying a target local process at least in part by translating the virtual process identifier into a local process identifier that corresponds with the target local process; and means for causing the at least one memory operation to be performed against a region of memory associated with the target local process.

22

22. The system of claim 21 , further comprising means for traversing a map to identify a local process that corresponds with the virtual process identifier.

23

23. The system of claim 22 , wherein the packet further includes a job tag, the job tag being associated with one or more local processes.

24

24. The system of claim 23 , further comprising: means for determining a base process address based on the job tag; and means for identifying the target local process by summing the base process address and the virtual process identifier.

Patent Metadata

Filing Date

Unknown

Publication Date

December 26, 2017

Inventors

Keith Underwood
Charles F. Giefer
David Addison

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