Method, Apparatus and Instructions for Parallel Data Conversions

1. A system comprising: at least one reduced instruction set computer (RISC) processor; a system memory to store instructions to be processed by the RISC processor; a memory controller to couple the RISC processor to the system memory over a system memory bus; and a network interface to couple the RISC processor to a network; the RISC processor comprising: a register file, within the RISC processor, including a first packed data register and a second packed data register; a register renamer within the RISC processor; a decoder, within the RISC processor, to decode the instructions, the instructions to include a first instruction; a scheduler, within the RISC processor, to queue operations that correspond to the instructions for execution; and execution logic, within the RISC processor, coupled to the decoder, the register renamer, and the scheduler, the execution logic to perform out-of-order execution of at least some of the instructions; wherein, responsive to a decode of the first instruction by the decoder, the execution logic is to convert a first plurality of packed signed data elements to be stored in the first packed data register to a second plurality of packed unsigned data elements in the second packed data register, one or more of the second plurality of packed unsigned data elements to be saturated; the first plurality of packed signed data elements to include floating point data elements and the second plurality of packed unsigned data elements to include integer data elements; at least one of the first plurality of packed signed data elements to have a first number of bits, at least one of the second plurality of packed unsigned data elements to have a second number of bits, wherein the second number of bits is one half the first number of bits.

2. The system as in claim 1 , wherein the first number of bits is 64 and the second number of bits is 32.

3. The system as in claim 1 , wherein the one or more of the second plurality of packed unsigned data elements is to be saturated if a condition is satisfied.

4. A system comprising: at least one reduced instruction set computer (RISC) processor; a system memory to store instructions to be processed by the RISC processor; a memory controller to couple the RISC processor to the system memory over a system memory bus; and a network interface to couple the RISC processor to a network; the RISC processor comprising: a register file, within the RISC processor, including a first packed data register and a second packed data register; a register renamer within the RISC processor; a decoder, within the RISC processor, to decode the instructions, the instructions to include a first instruction; a scheduler, within the RISC processor, to queue operations that correspond to the instructions for execution; and an execution unit, coupled to the decoder, the register renamer, and the scheduler, the execution unit to perform out-of-order execution of at least some of the instructions; wherein, responsive to a decode of the first instruction by the decoder, the execution unit is to convert a first plurality of packed signed data elements to be stored in the first packed data register to a second plurality of packed unsigned data elements in the second packed data register, one or more of the second plurality of packed unsigned data elements to be saturated; the first plurality of packed signed data elements to be floating point data elements and the second plurality of packed unsigned data elements to be integer data elements; each of the first plurality of packed signed data elements to have a first number of bits, each of the second plurality of packed unsigned data elements to have a second number of bits, wherein the second number of bits is one half the first number of bits.

5. The system as in claim 4 , wherein the first number of bits is 64 and the second number of bits is 32.

6. The system as in claim 4 , wherein the one or more of the second plurality of packed unsigned data elements is to be saturated if a condition is satisfied.