Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A system comprising: at least one reduced instruction set computer (RISC) processor; a system memory to store instructions to be processed by the RISC processor; a memory controller to couple the RISC processor to the system memory over a system memory bus; and a network interface to couple the RISC processor to a network; the RISC processor comprising: a register file, within the RISC processor, including a first packed data register and a second packed data register; a register renamer within the RISC processor; a decoder, within the RISC processor, to decode the instructions, the instructions to include a first instruction; a scheduler, within the RISC processor, to queue operations that correspond to the instructions for execution; and execution logic, within the RISC processor, coupled to the decoder, the register renamer, and the scheduler, the execution logic to perform out-of-order execution of at least some of the instructions; wherein, responsive to a decode of the first instruction by the decoder, the execution logic is to convert a first plurality of packed signed data elements to be stored in the first packed data register to a second plurality of packed unsigned data elements in the second packed data register, one or more of the second plurality of packed unsigned data elements to be saturated; the first plurality of packed signed data elements to include floating point data elements and the second plurality of packed unsigned data elements to include integer data elements; at least one of the first plurality of packed signed data elements to have a first number of bits, at least one of the second plurality of packed unsigned data elements to have a second number of bits, wherein the second number of bits is one half the first number of bits.
A computer system uses a RISC processor to convert packed floating-point data to packed unsigned integer data. The system includes a RISC processor, memory, memory controller, and network interface. Inside the processor, a register file holds data registers, including a first register for signed floating-point numbers and a second register for unsigned integers. Instructions are decoded, scheduled, and executed out-of-order. A specific instruction triggers the conversion of multiple signed floating-point values from the first register into unsigned integer values in the second register. The unsigned integer values can be saturated, and the unsigned integers use half the bits of the original floating-point values.
2. The system as in claim 1 , wherein the first number of bits is 64 and the second number of bits is 32.
The system described previously converts packed floating-point data to packed unsigned integer data using a RISC processor. Specifically, the floating-point numbers are 64 bits each, and the converted unsigned integers are 32 bits each. The system includes a RISC processor, memory, memory controller, and network interface. Inside the processor, a register file holds data registers, including a first register for signed floating-point numbers and a second register for unsigned integers. Instructions are decoded, scheduled, and executed out-of-order. A specific instruction triggers the conversion of multiple signed floating-point values from the first register into unsigned integer values in the second register. The unsigned integer values can be saturated.
3. The system as in claim 1 , wherein the one or more of the second plurality of packed unsigned data elements is to be saturated if a condition is satisfied.
The system described previously converts packed floating-point data to packed unsigned integer data using a RISC processor. The conversion of floating-point values to unsigned integers can result in saturation if a condition is met. The system includes a RISC processor, memory, memory controller, and network interface. Inside the processor, a register file holds data registers, including a first register for signed floating-point numbers and a second register for unsigned integers. Instructions are decoded, scheduled, and executed out-of-order. A specific instruction triggers the conversion of multiple signed floating-point values from the first register into unsigned integer values in the second register. The unsigned integers use half the bits of the original floating-point values.
4. A system comprising: at least one reduced instruction set computer (RISC) processor; a system memory to store instructions to be processed by the RISC processor; a memory controller to couple the RISC processor to the system memory over a system memory bus; and a network interface to couple the RISC processor to a network; the RISC processor comprising: a register file, within the RISC processor, including a first packed data register and a second packed data register; a register renamer within the RISC processor; a decoder, within the RISC processor, to decode the instructions, the instructions to include a first instruction; a scheduler, within the RISC processor, to queue operations that correspond to the instructions for execution; and an execution unit, coupled to the decoder, the register renamer, and the scheduler, the execution unit to perform out-of-order execution of at least some of the instructions; wherein, responsive to a decode of the first instruction by the decoder, the execution unit is to convert a first plurality of packed signed data elements to be stored in the first packed data register to a second plurality of packed unsigned data elements in the second packed data register, one or more of the second plurality of packed unsigned data elements to be saturated; the first plurality of packed signed data elements to be floating point data elements and the second plurality of packed unsigned data elements to be integer data elements; each of the first plurality of packed signed data elements to have a first number of bits, each of the second plurality of packed unsigned data elements to have a second number of bits, wherein the second number of bits is one half the first number of bits.
A computer system uses a RISC processor to convert packed floating-point data to packed unsigned integer data. The system includes a RISC processor, memory, memory controller, and network interface. Inside the processor, a register file holds data registers, including a first register for signed floating-point numbers and a second register for unsigned integers. Instructions are decoded, scheduled, and executed out-of-order by an execution unit. A specific instruction triggers the conversion of multiple signed floating-point values from the first register into unsigned integer values in the second register. The unsigned integer values can be saturated, and the unsigned integers use half the bits of the original floating-point values.
5. The system as in claim 4 , wherein the first number of bits is 64 and the second number of bits is 32.
The system described previously converts packed floating-point data to packed unsigned integer data using a RISC processor. Specifically, the floating-point numbers are 64 bits each, and the converted unsigned integers are 32 bits each. The system includes a RISC processor, memory, memory controller, and network interface. Inside the processor, a register file holds data registers, including a first register for signed floating-point numbers and a second register for unsigned integers. Instructions are decoded, scheduled, and executed out-of-order by an execution unit. A specific instruction triggers the conversion of multiple signed floating-point values from the first register into unsigned integer values in the second register. The unsigned integer values can be saturated.
6. The system as in claim 4 , wherein the one or more of the second plurality of packed unsigned data elements is to be saturated if a condition is satisfied.
The system described previously converts packed floating-point data to packed unsigned integer data using a RISC processor. The conversion of floating-point values to unsigned integers can result in saturation if a condition is met. The system includes a RISC processor, memory, memory controller, and network interface. Inside the processor, a register file holds data registers, including a first register for signed floating-point numbers and a second register for unsigned integers. Instructions are decoded, scheduled, and executed out-of-order by an execution unit. A specific instruction triggers the conversion of multiple signed floating-point values from the first register into unsigned integer values in the second register. The unsigned integers use half the bits of the original floating-point values.
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December 26, 2017
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