Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An apparatus for transmitting broadcast signals, the apparatus comprising: an encoder to encode Data Pipe (DP) data according to a 16200 bits codeword and an 11/15 code rate based on addresses in a parity check matrix, wherein the encoded DP data comprises information bits and parity bits; a frame builder to build at least one signal frame by mapping the encoded DP data; modulator to modulate data in the built signal frame by an Orthogonal Frequency Division Multiplexing (OFDM) method; a preamble inserter to insert a preamble at a beginning of each signal frame in a time domain; and a transmitter to transmit the broadcast signals having the preamble and the modulated data, wherein the DP data is encoded by: adding the information bits in groups of 360 information bits corresponding to each row of the parity check matrix to the parity bits of which addresses are based on values of entries in each row of the parity check matrix, where the parity check matrix is: 49 719 784 794 968 2382 2685 2873 2974 2995 3540 4179 272 281 374 1279 2034 2067 2112 3429 3613 3815 3838 4216 206 714 820 1800 1925 2147 2168 2769 2806 3253 3415 4311 62 159 166 605 1496 1711 2652 3016 3347 3517 3654 4113 363 733 1118 2062 2613 2736 3143 3427 3664 4100 4157 4314 57 142 436 983 1364 2105 2113 3074 3639 3835 4164 4242 870 921 950 1212 1861 2128 2707 2993 3730 3968 3983 4227 185 2684 3263 2035 2123 2913 883 2221 3521 1344 1773 4132 438 3178 3650 543 756 1639 1057 2337 2898 171 3298 3929 1626 2960 3503 484 3050 3323 2283 2336 4189 2732 4132 4318 225 2335 3497 600 2246 2658 1240 2790 3020 301 1097 3539 1222 1267 2594 1364 2004 3603 1142 1185 2147 564 1505 2086 697 991 2908 1467 2073 3462 2574 2818 3637 748 2577 2772 1151 1419 4129 164 1238 3401 ; and updating each k th parity bit by summing with each (k−1) th parity bit in the parity bits, where k is an integer greater than zero.
2. The apparatus of claim 1 , wherein the preamble includes emergency alert information for an emergency alert.
This invention relates to communication systems, specifically apparatuses for transmitting emergency alerts. The problem addressed is the need for efficient and reliable dissemination of emergency alert information to ensure public safety. The apparatus includes a transmitter configured to send a preamble containing emergency alert information. The preamble is structured to facilitate rapid detection and processing by receiving devices, ensuring timely delivery of critical alerts. The emergency alert information within the preamble may include details such as the type of emergency, affected areas, and recommended actions. This design allows for quick identification and prioritization of emergency messages, reducing response times and improving public safety outcomes. The apparatus may also include additional components to enhance signal robustness, such as error correction mechanisms or redundancy features, to ensure reliable transmission even in challenging conditions. By integrating emergency alert information directly into the preamble, the system minimizes delays and ensures that critical data is available as soon as the signal is received, improving the effectiveness of emergency communication networks.
3. The apparatus of claim 1 , wherein the addresses of the parity bits are represented as q(i, j, 1), wherein q(i, j, 1)=q(i ,j , 0)+Q_1dpc*1(mod 4320), and wherein q (i ,j, 0) is a value of a j-th entry in an i-th row of the parity check matrix, Q_1dpc is 12, and 1 is an index of each information bit in the group of 360 information bits.
This invention relates to error correction coding, specifically a method for addressing parity bits in a parity check matrix used in low-density parity-check (LDPC) codes. The problem addressed is efficiently organizing parity bits to improve decoding performance and reduce complexity in error correction systems. The apparatus includes a parity check matrix with a structured arrangement of parity bits, where the addresses of these bits are calculated using a specific formula. The formula defines the address of a parity bit as q(i, j, 1), where q(i, j, 0) is the base address of the j-th entry in the i-th row of the parity check matrix. The address is adjusted by adding a product of a constant Q_1dpc (set to 12) and an index 1, modulo 4320. This ensures that parity bits are distributed in a way that optimizes decoding efficiency and minimizes computational overhead. The method is particularly useful in communication systems requiring robust error correction, such as wireless networks or data storage devices, where reliable data transmission and retrieval are critical. The structured addressing scheme helps maintain low latency and high throughput during decoding operations.
4. An apparatus for receiving broadcast signals, the apparatus comprising: a receiver to receive broadcast signals having a preamble and modulated data in signal frames; a de-modulator to de-modulate the modulated data by an Orthogonal Frequency Division Multiplexing (OFDM) method; a parser to parse at least one signal frame by de-mapping Data Pipe (DP) data; and a decoder to decode the de-mapped DP data according to a 16200 bits codeword and an 11/15 code rate based on addresses in a parity check matrix, wherein the de-mapped DP data includes parity bits generated by: adding information bits in groups of 360 information bits corresponding to each row of the parity check matrix to the parity bits of which addresses are based on values of entries in each row of the parity check matrix, where the parity check matrix is: 49 719 784 794 968 2382 2685 2873 2974 2995 3540 4179 272 281 374 1279 2034 2067 2112 3429 3613 3815 3838 4216 206 714 820 1800 1925 2147 2168 2769 2806 3253 3415 4311 62 159 166 605 1496 1711 2652 3016 3347 3517 3654 4113 363 733 1118 2062 2613 2736 3143 3427 3664 4100 4157 4314 57 142 436 983 1364 2105 2113 3074 3639 3835 4164 4242 870 921 950 1212 1861 2128 2707 2993 3730 3968 3983 4227 185 2684 3263 2035 2123 2913 883 2221 3521 1344 1773 4132 438 3178 3650 543 756 1639 1057 2337 2898 171 3298 3929 1626 2960 3503 484 3050 3323 2283 2336 4189 2732 4132 4318 225 2335 3497 600 2246 2658 1240 2790 3020 301 1097 3539 1222 1267 2594 1364 2004 3603 1142 1185 2147 564 1505 2086 697 991 2908 1467 2073 3462 2574 2818 3637 748 2577 2772 1151 1419 4129 164 1238 3401 ; and updating each k th parity bit by summing with each (k−1) th parity bit in the parity bits, where k is an integer greater than zero.
This invention relates to a broadcast signal receiver apparatus designed to process signals using Orthogonal Frequency Division Multiplexing (OFDM) and a specific error correction coding scheme. The apparatus receives broadcast signals containing a preamble and modulated data organized into signal frames. The receiver demodulates the OFDM-modulated data and parses the signal frames to extract Data Pipe (DP) data. The extracted DP data is then decoded using a 16200-bit codeword with an 11/15 code rate, based on addresses defined in a predefined parity check matrix. The parity check matrix specifies the positions of parity bits generated by adding groups of 360 information bits to corresponding parity bit addresses. The parity bits are further processed by updating each k-th parity bit by summing it with the (k-1)-th parity bit, where k is a positive integer. The parity check matrix includes specific numerical entries that determine the parity bit generation and updating process, ensuring efficient error correction in the received broadcast signals. This system enhances data reliability in broadcast transmissions by leveraging structured parity bit generation and updating mechanisms.
5. The apparatus of claim 4 , wherein the preamble includes emergency alert information for an emergency alert.
This invention relates to communication systems, specifically apparatuses for transmitting emergency alert information. The problem addressed is the need for efficient and reliable dissemination of emergency alerts to ensure public safety. The apparatus includes a transmitter configured to send a preamble containing emergency alert information. The preamble is structured to facilitate rapid detection and processing by receiving devices, ensuring timely delivery of critical alerts. The apparatus may also include a processor to encode the alert data into the preamble, optimizing transmission efficiency. The preamble may further include synchronization signals to help receiving devices accurately decode the alert information. The system ensures that emergency alerts are prioritized and transmitted with minimal delay, improving response times during critical situations. The apparatus may be integrated into broadcast systems, cellular networks, or other communication infrastructures to enhance alert distribution capabilities. The invention focuses on improving the reliability and speed of emergency alert transmissions, addressing challenges in existing systems where delays or failures can have severe consequences. The apparatus may also include error correction mechanisms to ensure the integrity of transmitted alert data, further enhancing the robustness of the system.
6. The apparatus of claim 4 , wherein the addresses of the parity bits are represented as q(i, j, 1), wherein q(i, j, 1)=q(i, j, 0)+Q_1dpc*1 (mod 4320), and wherein q (i, j, 0) is a value of a j-th entry in an i-th row of the parity check matrix, Q_1dpc is 12, and 1 is an index of each information bit in the group of 360 information bits.
This invention relates to error correction coding, specifically a method for addressing parity bits in a parity check matrix used for low-density parity-check (LDPC) codes. The problem addressed is efficiently organizing parity bits to improve decoding performance and reduce complexity in communication systems, such as those used in digital broadcasting or data storage. The apparatus includes a parity check matrix with multiple rows and columns, where each entry in the matrix corresponds to a parity bit address. The addresses of the parity bits are calculated using a specific formula: q(i, j, 1) = q(i, j, 0) + Q_1dpc * 1 (mod 4320). Here, q(i, j, 0) is the base address of the j-th entry in the i-th row of the parity check matrix, Q_1dpc is a fixed value of 12, and 1 represents the index of each information bit in a group of 360 information bits. This formula ensures that parity bits are systematically distributed across the matrix, optimizing the decoding process by reducing redundancy and improving error correction efficiency. The apparatus further includes a memory for storing the parity check matrix and a processor for generating and applying the parity bit addresses during encoding and decoding. The method ensures that parity bits are correctly mapped to their respective positions, enhancing the reliability of error detection and correction in data transmission or storage systems. The use of modular arithmetic (mod 4320) ensures that the addresses remain within a defined range, preventing overflow and maintaining consistency in the parity check process.
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January 16, 2018
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