Scan Driver for Outputting a Sensing Scan Signal to Detect a Driving Current of Pixels and Display Device Having the Same

1. A scan driver comprising: a plurality of decoder type stages configured to respectively output a plurality scan signals, an n-th stage of the decoder type stages comprising: a first input block configured to provide a first direct current (DC) voltage to a first node in response to a plurality of selection signals; a pull-down block configured to provide a second DC voltage to the first node and to pull down a first node voltage; a second input block configured to reduce a voltage drop of a second node voltage when a scan signal is output, and to provide the second DC voltage to a second node in response to the selection signals; a buffer block configured to output the first node voltage as a buffer output voltage in response to the first node voltage and the second node voltage; and an output block configured to output the scan signal in response to the second node voltage, the buffer output voltage, and a first clock signal, wherein n is a positive integer.

2. The scan driver of claim 1 , wherein the buffer block comprises: a first buffer switch; and a second buffer switch connected in series to the first buffer switch, and wherein the buffer block is configured to provide the buffer output voltage to the output block.

3. The scan driver of claim 2 , wherein the first buffer switch comprises: a gate electrode connected to the second node; a source electrode to which the first DC voltage is configured to be applied; and a drain electrode connected to a third node, and wherein the second buffer switch comprises: a gate electrode connected to the first node; a source electrode connected to the drain electrode of the first buffer switch; and a drain electrode to which the second DC voltage is configured to be applied.

4. The scan driver of claim 1 , wherein the first input block comprises a first switch, a second switch, and a third switch connected in series to each other, and wherein the second input block comprises a fourth switch, a fifth switch, a sixth switch, and a cutoff switch connected in series to each other.

5. The scan driver of claim 4 , wherein the first switch comprises: a gate electrode to which a first selection signal is configured to be applied; a source electrode to which the first DC voltage is configured to be applied; and a drain electrode connected to the second switch, wherein the second switch comprises: a gate electrode to which a second selection signal is configured to be applied; a source electrode connected to the drain electrode of the first switch; and a drain electrode connected to the third switch, and wherein the third switch comprises: a gate electrode to which a third selection signal is configured to be applied; a source electrode connected to the drain electrode of the second switch; and a drain electrode connected to the first node.

6. The scan driver of claim 4 , wherein the fourth switch comprises: a gate electrode to which a first selection signal is configured to be applied; a source electrode connected to the second node; and a drain electrode connected to the fifth switch, wherein the fifth switch comprises: a gate electrode to which a second selection signal is configured to be applied; a source electrode connected to the drain electrode of the fourth switch; and a drain electrode connected to the sixth switch, wherein the sixth switch comprises: a gate electrode to which a third selection signal is configured to be applied; a source electrode connected to the drain electrode of the fifth switch; and a drain electrode connected to the cutoff switch, and wherein the cutoff switch comprises: a gate electrode to which a second clock signal is configured to be applied; a source electrode connected to the drain electrode of the sixth switch; and a drain electrode to which the second DC voltage is configured to be applied.

7. The scan driver of claim 6 , wherein the second clock signal comprises a signal inverted from the first clock signal.

8. The scan driver of claim 6 , further comprising an inverting block configured to generate the second clock signal based on the first clock signal, and configured to apply the second clock signal to the gate electrode of the cutoff switch.

9. The scan driver of claim 8 , wherein the inverting block comprises a first inverting switch and a second inverting switch connected in series to each other, wherein the first inverting switch comprises: a gate electrode to which the first clock signal is configured to be applied; a source electrode to which the first DC voltage is configured to be applied; and a drain electrode connected to the second inverting switch, and wherein the second inverting switch comprises: a gate electrode to which the second DC voltage is configured to be applied; a source electrode connected to the drain electrode of the first inverting switch; and a drain electrode connected to the gate electrode of the second inverting switch.

10. The scan driver of claim 9 , wherein the gate electrode of the cutoff switch is connected to the drain electrode of the first inverting switch and to the source electrode of the second inverting switch.

11. The scan driver of claim 1 , wherein the output block comprises: a first output switch comprising: a gate electrode to which the buffer output voltage is configured to be applied; a source electrode connected to the second node; and a drain electrode connected to an output terminal; a second output switch comprising: a gate electrode connected to a third node; a source electrode to which the first DC voltage is configured to be applied; and a drain electrode connected to the output terminal; a third output switch comprising: a gate electrode connected to the second node; a source electrode connected to the output terminal; and a drain electrode to which the first clock signal is configured to be applied; and a capacitor connected between the second node and the third output switch.

12. The scan driver of claim 11 , wherein the second node voltage is configured to be bootstrapped by the capacitor when the third output switch is turned on, so that the scan signal is output.

13. The scan driver of claim 1 , wherein the pull-down block comprises a bootstrap circuit, and wherein the pull-down block is configured to pull down the first node voltage into the second DC voltage when an operation in which the first input block applies the first DC voltage to the first node is stopped.

14. The scan driver of claim 1 , wherein the second DC voltage is lower than the first DC voltage.

15. A display device comprising: a display panel comprising a plurality of pixels; a data driver configured to provide a data signal to the pixels; a first scan driver configured to provide a scan signal to the pixels; and a second scan driver comprising a decoder type scan driver, and configured to provide a sensing scan signal to the pixels to detect a driving current of each of the pixels in a set sensing period, wherein an n-th stage of the second scan driver comprises: a first input block configured to provide a first direct current (DC) voltage to a first node in response to a plurality of selection signals; a pull-down block configured to provide a second DC voltage to the first node and to pull down a first node voltage; a second input block configured to reduce a voltage drop of a second node voltage when the sensing scan signal is output, and to provide the second DC voltage to a second node in response to the selection signals; a buffer block configured to output the first node voltage as a buffer output voltage in response to the first node voltage and the second node voltage; and an output block configured to output the sensing scan signal in response to the second node voltage, the buffer output voltage, and a first clock signal, wherein n is a positive integer.

16. The display device of claim 15 , wherein the second scan driver is configured to select a sensing scan line, and is configured to output the sensing scan signal to the sensing scan line based on turn-on voltage levels of the selection signals.

17. The display device of claim 15 , wherein the buffer block comprises a first buffer switch and a second buffer switch connected in series to each other, and wherein the buffer block is configured to provide the buffer output voltage to the output block.

18. The display device of claim 17 , wherein the first buffer switch comprises: a gate electrode connected to the second node; a source electrode to which the first DC voltage is configured to be applied; and a drain electrode connected to a third node, and wherein the second buffer switch comprises: a gate electrode connected to the first node; a source electrode connected to the drain electrode of the first buffer switch; and a drain electrode to which the second DC voltage is configured to be applied.

19. The display device of claim 15 , wherein the second input block comprises a cutoff switch configured to reduce the voltage drop of the second node voltage based on a second clock signal comprising a signal inverted from the first clock signal when the sensing scan signal is output.

20. The display device of claim 15 , further comprising a controller configured to control the data driver, the first scan driver, and the second scan driver.