Method and Universal Interface Chip for Achieving High-Speed Data Transmission

1. A method for achieving high-speed data transmission applicable to a universal interface chip, comprising steps of: A, a universal interface chip of a transmitting terminal monitoring and receiving a data packet to transmit; B, the universal interface chip of the transmitting terminal repacking the received data packet according to a preset bit width and adding a check code, and transmitting the repacked data packet to a universal interface chip of a receiving terminal; C, the universal interface chip of the transmitting terminal receiving a response message from the universal interface chip of the receiving terminal; and D, the universal interface chip of the transmitting terminal implementing a corresponding process on the data packet according to the received response message, wherein, the step B comprises: the universal interface chip of the transmitting terminal regulating a data transmission queue for the data to be transmitted according to a preset arbitration policy: the universal interface chip of the transmitting terminal repacking a data packet in a highest priority order in a current data transmission queue according to a preset bit width and adding a check code: and the universal interface chip of the transmitting terminal transmitting the repacked data packet to the universal interface chip of the receiving terminal; wherein, the arbitration policy comprises: configuring data transmission priorities, and firstly transmitting data with a higher priority; when the data has same priority, firstly transmitting short data; when the data has the same priority and same data length, firstly transmitting data which is firstly arrived; and/or when the data has the same priority, the same data length, and same incoming time node, firstly transmitting data from a data source where data transmission is not implemented for a longest time.

2. The method for achieving high-speed data transmission according to claim 1 , further comprising steps of: E, the universal interface chip of the receiving terminal receiving the data packet transmitted from the universal interface chip of the transmitting terminal; and F, the universal interface chip of the receiving terminal unpacking and checking the received data packet, and transmitting a corresponding response message to the universal interface chip of the transmitting terminal according to a check result.

3. The method for achieving high-speed data transmission according to claim 2 , wherein, the step F comprises: the universal interface chip of the receiving terminal unpacking the received data packet, and checking whether the received data packet is correct; when it is checked that the data packet is correct, the universal interface chip of the receiving terminal transmitting the data packet checked to be correct to a corresponding sub-system, and returning a reception correct response message to the universal interface chip of the transmitting terminal; and when it is checked that the data packet is incorrect, the universal interface chip of the receiving terminal discarding the data packet checked to be incorrect, and returning a reception incorrect response message to the universal interface chip of the transmitting terminal.

4. The method for achieving high-speed data transmission according to claim 3 , wherein, the step D comprises: when the universal interface chip of the transmitting terminal receives the reception correct response message, the universal interface chip of the transmitting terminal releasing internal occupied resources to continue to transmit other data packets to be transmitted; and when the reception incorrect response message is received, retransmitting the corresponding data packet.

5. A universal interface chip for achieving high-speed data transmission, comprising a packing arbitration hardware module and a packing hardware module, wherein, the packing arbitration hardware module is configured to monitor and receive a data packet to be transmitted; and the packing hardware module is configured to repack the received data packet according to a preset bit width and add a check code, transmit the repacked data packet to a universal interface chip of a receiving terminal, receive a response message from the universal interface chip of the receiving terminal, and implement a corresponding process on the data packet according to the received response message, wherein, the packing hardware module is configured to repack the received data packet according to a preset bit width and add a check code, and transmit the repacked data packet to a universal interface chip of a receiving terminal by a following mode: regulating a data transmission queue for the data to be transmitted according to a preset arbitration policy; repacking a data packet in a highest priority order in a current data transmission queue according to the preset bit width and adding a check code; and transmitting the repacked data packet to the universal interface chip of the receiving terminal, wherein, the arbitration policy comprises: configuring data transmission priorities, and firstly transmitting data with a higher priority; when the data has a same priority, firstly transmitting short data; when the data has the same priority and a same data length, firstly transmitting data which is firstly arrived; and/or when the data has the same priority, the same data length, and a same incoming time node, firstly transmitting data from a data source where data transmission is not implemented for a longest time.

6. The universal interface chip according to claim 5 , wherein, the universal interface chip further comprises a packet receiving hardware module and an unpacking hardware module, wherein, the packet receiving hardware module is configured to receive the data packet transmitted from the universal interface chip of the transmitting terminal; and the unpacking hardware module is configured to unpack and check the received data packet, and transmit a corresponding response message to the universal interface chip of the transmitting terminal according to a check result.

7. The universal interface chip according to claim 6 , wherein, the unpacking hardware module is configured to unpack and check the received data packet, and transmit a corresponding response message to the universal interface chip of the transmitting terminal according to a check result by a following mode: unpacking the received data packet, and checking whether the received data packet is correct; when it is checked that the data packet is correct, transmitting the data packet check to be correct to a corresponding sub-system, and returning a reception correct response message to the universal interface chip of the transmitting terminal; and when it is checked that the data packet is incorrect, discarding the data packet checked to be incorrect, and returning a reception incorrect response message to the universal interface chip of the transmitting terminal.

8. The universal interface chip according to claim 7 , wherein, the packing hardware module is configured to implement a corresponding process on the data packet according to the received response message by a following mode: when the reception correct response message is received, releasing internal occupied resources to continue to transmit other data packets to be transmitted; and when the reception incorrect response message is received, retransmitting the corresponding data packet.