Output Circuit and Switching Circuit of Display Driving Device

1. An output circuit of a display driving device, comprising: an output buffer unit configured to buffer a pair of first and second input signals having different polarities and output a pair of first and second output signals; and a switching unit configured to transmit the pair of first and second output signals to a pair of first and second output terminals through a direct path or a cross path during an output period, and charge-share the pair of output terminals using a middle voltage of a pull-up voltage and a pull-down voltage of the output buffer unit during a charge-sharing period, wherein the switching unit comprises: a first switching circuit configured to transmit the first output signal to the first terminal through first and second switches coupled in series; a second switching circuit configured to transmit the first output signal to the second terminal through third and fourth switches coupled in series; a third switching circuit configured to precharge a node between the third and fourth switches to the middle voltage at the output period, the third and fourth switches being disabled when the first and second switches transmit the first output signal to the first terminal; and a fourth switching circuit configured to precharge a node between the first and second switches to the middle voltage at the output period, the first and second switches being disabled when the third and fourth switches transmit the first output signal to the second terminal.

2. The output circuit of claim 1 , wherein the switching unit precharges a specific node of the direct path or the cross path which is disabled at the output period to the middle voltage.

3. The output circuit of claim 1 , wherein the middle voltage is set to an average value of the pull-up voltage and the pull-down voltage, which are used for driving the output buffer unit.

4. The output circuit of claim 1 , wherein the switching unit comprises switches using transistors having a withstanding voltage corresponding to a low voltage, and is configured to drive in the range of the pull-up voltage and the middle voltage or the middle voltage and the pull-down voltage, which are used for driving the output buffer unit.

5. The output circuit of claim 1 , wherein the second switch comprises a first PMOS transistor and a first NMOS transistor, each of which has a source and body coupled to each other, and the fourth switch comprises a second PMOS transistor and a second NMOS transistor, each of which has a source and body coupled to each other.

6. The output circuit of claim 1 , wherein the second switch comprises a first PMOS transistor and a first NMOS transistor, and the fourth switch comprises a second PMOS transistor and a second NMOS transistor, and the first and second PMOS transistors or the first and second NMOS transistors are configured to selectively turn on in response to the polarity state of the output period during the charge-sharing period.

7. An output circuit of a display driving device, comprising: an output buffer unit configured to buffer a pair of first and second input signals having different polarities and output a pair of first and second output signals; a first switching unit configured to transmit the pair of first and second output signals using a direct path or cross path during an output period; a second switching unit configured to transmit the pair of first and second output signals received from the first switching unit to a pair of first and second output terminals, and charge-share the pair of output terminals to a middle voltage of a pull-up voltage and a pull-down voltage of the output buffer when the first switching unit is disabled; and a precharge unit configured to precharge a node between the first and second switching units to the middle voltage, wherein the first switching unit comprises a first switch providing the direct path and a third switch providing the cross path, wherein the second switching unit comprises a second switch serially coupled to the first switch and a fourth switch serially coupled to the third switch, wherein the first and second switches transmit the first output signal to the first output terminal, the third and fourth switches transmit the first output signal to the second output terminal, and wherein the precharge unit precharges a node between the third and fourth switches to the middle voltage at the output period, the third and fourth switches being disabled when the first and second switches transmit the first output signal to the first terminal, and precharges a node between the first and second switches to the middle voltage at the output period, the first and second switches being disabled when the third and fourth switches transmit the first output signal to the second terminal.

8. The output circuit of claim 7 , wherein the middle voltage is set to an average value of the pull-up voltage and the pull-down voltage of the output buffer unit.

9. The output circuit of claim 7 , wherein the first switching unit, the second switching unit, and the precharge unit comprise switches using transistors having a withstanding voltage corresponding to a low voltage, and are configured to drive in the range of a pull-up voltage and a middle voltage or the middle voltage and a pull-down voltage, which are used for driving the output buffer unit.

10. A switching circuit of a display driving circuit, comprising: first and second switches serially coupled and configured to transmit an output signal of an output buffer unit to a first output terminal through a direct path during an output period; third and fourth switches serially connected configured to transmit the output signal of the output buffer unit to a second output terminal through a cross path during the output period; a fifth switch configured to precharge a node between the third and fourth switches to a middle voltage of a pull-up voltage and a pull-down voltage of the output buffer unit at the output period, the third and fourth switches being disabled when the first and second switches transmit the output signal to the first terminal, and a sixth switch configured to precharge a node between the first and second switches to the middle voltage at the output period, the first and second switches being disabled when the third and fourth switches transmit the output signal to the second terminal.

11. The output circuit of claim 10 , wherein the second and third switches are configured to charge-share the first output terminal to the middle voltage when the first switch is disabled.

12. The output circuit of claim 10 , wherein the middle voltage is set to an average voltage of the pull-up voltage and the pull-down voltage of the output buffer unit.

13. The output circuit of claim 10 , wherein the first to sixth switches comprise transistors having a withstanding voltage corresponding to a low voltage, and are configured to drive in the range of a pull-up voltage and a middle voltage or the middle voltage and a pull-down voltage, which are used for driving the output buffer unit.