Ic and Process Shifting Compressed Data and Loading Scan Paths

1. A circuit comprising: (a) a serial compressed data (SCI) input terminal; (b) a CK clock terminal carrying a CK clock signal and a SC scan clock terminal carrying a SC scan clock signal; (c) a plurality of scan paths (SP), each of the scan paths including a plurality of flip flops coupled in series and having an scan input (SI), a SC scan clock input coupled to the SC scan clock terminal and an scan output (SO); and (d) an input shift register (ISR) having an input coupled to the serial compressed data (SCI) input terminal, a plurality of outputs coupled to the scan inputs, and a CK clock input coupled to the CK clock terminal, including shifting serial compressed data into the input shift register with the CK clock signal while not shifting data in the scan paths with the SC scan clock signal, and loading data from the input shift register into the scan paths within one cycle of the SC scan clock signal after the serial compressed data is shifted into the input shift register with the CK clock signal.

2. The circuit of claim 1 including a decompressor having inputs coupled to the outputs of the input shift register and outputs coupled to the scan inputs.

3. The circuit of claim 2 including: parallel compressed data (PCI) inputs; and a multiplexer having first inputs coupled to the outputs of the input shift register, second inputs coupled to the parallel data (PCI) inputs, and outputs coupled to the decompressor inputs.

4. A process of operating an integrated circuit including (a) a serial compressed data (SCI) input terminal; (b) a CK clock terminal carrying a CK clock signal and a SC scan clock terminal carrying a SC scan clock signal; (c) a plurality of scan paths (SP), each of the scan paths including a plurality of flip flops coupled in series and having an scan input (SI) a SC scan clock signal input coupled to the SC scan clock terminal, and an scan output (SO); and (d) an input shift register (ISR) having an input coupled to the serial compressed data (SCI) input terminal, a plurality of outputs coupled to the scan inputs, and a CK clock input coupled to the CK clock terminal, the process comprising: (e) shifting serial compressed data into the input shift register with the CK clock signal while not shifting data in the scan paths with the SC scan clock signal; and (f) loading data from the input shift register into the scan paths within one cycle of the SC scan clock signal after the serial compressed data is shifted into the input shift register with the CK clock signal.

5. The process of claim 4 in which the integrated circuit includes a decompressor having inputs coupled to the outputs of the input shift register and outputs coupled to the scan inputs, the decompressor decompressing serial compressed data from the input shift register.

6. The process of claim 5 in which the integrated circuit includes: parallel compressed data (PCI) inputs; and a multiplexer having first inputs coupled to the outputs of the input shift register, second inputs coupled to the parallel data (PCI) inputs, and outputs coupled to the decompressor inputs.