Methods, Systems, and Articles of Manufacture for Simplifying an Electronic Design for Verification by Domain Reduction

1. A computer implemented method for simplifying an electronic design for verification by domain reduction, comprising: extracting, with an extraction mechanism that is stored at least partially in memory and includes or functions in conjunction with a computer processor or a processor core, one or more data flows for at least a portion of an electronic design under verification; constructing a comparison graph comprising tokens and edges for the at least the portion of the electronic design; reducing at least one original variable width of a plurality of signals in the one or more data flows to a reduced variable width at least by coloring the comparison graph with a number of colors; and performing one or more analyses for the plurality of signals in the at least the portion of the electronic design using at least the reduced variable width, rather than the at least one original variable width.

2. The computer implemented method of claim 1 , further comprising: reducing the domain size of the at least the portion of the electronic design based in part or in whole upon the number of colors; identifying the at least the portion of the electronic design; and identifying the tokens from the one or more data flows.

3. The computer implemented method of claim 2 , wherein the at least the portion of the electronic design does not include electronic design components that transform values of the tokens.

4. The computer implemented method of claim 1 , further comprising: identifying an electronic design component and a type of an operation for the electronic design component; identifying a first input for the electronic design component; and identifying one or more second inputs for the electronic design component that performs the operation on the first input and the one or more second inputs.

5. The computer implemented method of claim 4 , further comprising: updating the comparison graph by adding at least one edge between the first input and at least one second input of the one or more second inputs.

6. The computer implemented method of claim 4 , further comprising: identifying a first fanin cone for the first input; identifying one or more third tokens in the first fanin cone for the first input; and updating the comparison graph by adding at least one edge between at least one second input of the one or more second inputs and at least one third token of the one or more third tokens.

7. The computer implemented method of claim 4 , further comprising: identifying at least one second fanin cone for the one or more second inputs; identifying one or more fourth tokens in the at least one second fanin cone for the one or more second inputs; and updating the comparison graph by adding at least one edge between the first input and at least one fourth token of the one or more fourth tokens.

8. The computer implemented method of claim 1 , further comprising: identifying one or more implied relations for the at least the portion of the electronic design based in part or in whole upon the one or more data flows; identifying at least two tokens in the comparison graph based in part or in whole upon the one or more implied relations, wherein the at least two tokens are not directly or indirectly compared according to the one or more data flows; and updating the comparison graph by adding an implied edge between the at least two tokens.

9. The computer implemented method of claim 1 , further comprising: determining whether the comparison graph includes at least one conflict cycle; and applying one or more conflict resolution techniques.

10. The computer implemented method of claim 1 , coloring the comparison graph further comprising: determining the number of different colors for coloring the comparison graph based in part or in whole upon the one or more data flows; and assigning colors to the tokens in the comparison graph according to the one or more data flows.

11. The computer implemented method of claim 1 , further comprising: identifying a first clock cycle and a first data flow of the one or more data flows for the first clock cycle; and identifying one or more first tokens in the first data flow for the first clock cycle.

12. The computer implemented method of claim 11 , further comprising: identifying one or more first comparisons for the one or more first tokens from the first data flow of the first clock cycle; and generating a first comparison sub-graph for the first clock cycle at least by using the one or more first tokens and one or more edges connecting at least some of the one or more first tokens based in part or in whole upon the one or more first comparisons.

13. The computer implemented method of claim 12 , further comprising: identifying a second clock cycle and a second data flow of the one or more data flows of the second clock cycle; and identifying one or more second tokens in the second data flow for the second clock cycle.

14. The computer implemented method of claim 13 , further comprising: identifying one or more second comparisons for the one or more second tokens from the second data flow of the second clock cycle; and generating a second comparison sub-graph for the second clock cycle at least by using the one or more second tokens and one or more edges connecting at least some of the one or more second tokens based in part or in whole upon the one or more second comparisons.

15. The computer implemented method of claim 14 , further comprising: unrolling the at least the portion of the electronic design by adding at least one additional edge to connect the first comparison sub-graph and the second comparison sub-graph.

16. The computer implemented method of claim 14 , further comprising: identifying one or more implied relations between a first token in the first comparison sub-graph and a second token in the second comparison sub-graph; and updating the comparison graph by adding at least one implied edge based in part or in whole upon the one or more implied relations.

17. The computer implemented method of claim 14 , further comprising: collapsing the first comparison sub-graph upon the second comparison sub-graph for constructing the comparison graph.

18. The computer implemented method of claim 14 , further comprising: determining whether the comparison graph includes at least one conflict cycle; and applying one or more conflict resolution techniques.

19. The computer implemented method of claim 1 , coloring the comparison graph further comprising: determining a minimum number of different colors that, when used to color the comparison graph, satisfies the one or more data flows; and assigning the minimum number of different colors to the tokens of the comparison graph based in part or in whole upon the one or more data flows.

20. The computer implemented method of claim 19 , further comprising: determining a total count of bits for representing the tokens based in part or in whole upon the minimum number of different colors; representing the minimum number of different colors with a set of numbers; and reducing the domain size of the at least the portion of the electronic design by using the set of numbers.

21. A system for simplifying an electronic design for verification by domain reduction, comprising: at least one micro-processor or processor core of a computing system; a non-transitory computer accessible storage medium storing thereupon program code that includes a sequence of instructions that, when executed by the at least one micro-processor or processor core of the computing system, causes the at least one micro-processor or processor core at least to: extract one or more data flows for at least a portion of an electronic design under verification; construct a comparison graph comprising vertices and edges for the at least the portion of the electronic design; reduce at least one original variable width of a plurality of signals in the one or more data flows to a reduced variable width at least by coloring the comparison graph with a number of colors; and perform one or more analyses for the plurality of signals in the at least the portion of the electronic design using at least the reduced variable width, rather than the at least one original variable width.

22. The system of claim 21 , wherein the program code includes further instructions that, when executed by the at least one micro-processor or processor core, cause the at least one processor or processor core to: reduce the domain size of the at least the portion of the electronic design based in part or in whole upon the number of colors; identify an electronic design component and a type of an operation for the electronic design component; identify a first input for the electronic design component; and identify one or more second inputs for the electronic design component that performs the operation on the first input and the one or more second inputs.

23. The system of claim 22 , wherein the program code includes further instructions that, when executed by the at least one micro-processor or processor core, cause the at least one processor or processor core to: identify a first fanin cone for the first input; identify one or more third tokens in the first fanin cone for the first input; and update the comparison graph by adding at least one edge between at least one second input of the one or more second inputs and at least one third token of the one or more third tokens.

24. The system of claim 21 , wherein the program code includes further instructions that, when executed by the at least one micro-processor or processor core, cause the at least one processor or processor core to: identify one or more implied relations for the at least the portion of the electronic design based in part or in whole upon the one or more data flows; identify at least two tokens in the comparison graph based in part or in whole upon the one or more implied relations, wherein the at least two tokens are not directly or indirectly compared according to the one or more data flows; and update the comparison graph by adding an implied edge between the at least two tokens.

25. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a set of acts for simplifying an electronic design for verification by domain reduction, the set of acts comprising: extracting one or more data flows for at least a portion of an electronic design under verification; constructing a comparison graph comprising tokens and edges for the at least the portion of the electronic design; reducing at least one original variable width of a plurality of signals in the one or more data flows to a reduced variable width at least by coloring the comparison graph with a number of colors; and performing one or more analyses for the plurality of signals in the at least the portion of the electronic design using at least the reduced variable width, rather than the at least one original variable width.

26. The article of manufacture of claim 25 , the set of acts further comprising: reducing the domain size of the at least the portion of the electronic design based in part or in whole upon the number of colors; determining whether the comparison graph includes at least one conflict cycle; and applying one or more conflict resolution techniques.

27. The article of manufacture of claim 25 , the set of acts further comprising: identifying a first clock cycle and a first data flow of the one or more data flows for the first clock cycle; identifying one or more first tokens in the first data flow for the first clock cycle; identifying one or more first comparisons for the one or more first tokens from the first data flow of the first clock cycle; and generating a first comparison sub-graph for the first clock cycle at least by using the one or more first tokens and one or more edges connecting at least some of the one or more first tokens based in part or in whole upon the one or more first comparisons.

28. The article of manufacture of claim 27 , the set of acts further comprising: identifying a second clock cycle and a second data flow of the one or more data flows of the second clock cycle; identifying one or more second tokens in the second data flow for the second clock cycle; identifying one or more second comparisons for the one or more second tokens from the second data flow of the second clock cycle; and generating a second comparison sub-graph for the second clock cycle at least by using the one or more second tokens and one or more edges connecting at least some of the one or more second tokens based in part or in whole upon the one or more second comparisons.