Gate Driver on Array Circuit and Display Device

1. A gate driver on array (GOA) circuit, including a plurality of GOA units, each of the GOA units provided with an (n−1)th level input end, an (n+1)th level input end, a first clock signal input end, a second clock signal input end, a high voltage-level input end, a low voltage-level input end, and a output end, and comprising: a drive module electrically connected to the (n−1)th level input end and the (n+1)th level input end; a pull-down module electrically connected to the drive module, the first clock signal input end, and the high voltage-level input end; a pull-down output module electrically connected to the first clock signal input end, the high voltage-level input end, the low voltage-level input end, and the output end, wherein the pull-down output module comprises a circuit input end electrically connected to the drive module and the pull-down module, and a pull-down node electrically connected to the pull-down module; a pull-up output module electrically connected to the second clock signal input end and the output end, wherein the pull-up output module comprises a pull-up node electrically connected to the pull-down module; a first thin film transistor (TFT) including a gate electrically connected to the high voltage-level input end, a first electrode end electrically connected to the pull-up node of the pull-up output module, and a second electrode end electrically connected to the circuit input end of the pull-down output module; a second TFT including a gate electrically connected to the first clock signal input end, and a first electrode end electrically connected to the second electrode end of the first TFT; a third TFT including a first electrode end electrically connected to a second electrode end of the second TFT, and a second electrode end electrically connected to the pull-down node of the pull-down output module; a fourth TFT including a gate electrically connected to the circuit input end, and a first electrode end electrically connected to a gate of the third TFT; a fifth TFT including a gate electrically connected to a second electrode end of the fourth TFT, a first electrode end electrically connected to the first electrode end of the fourth TFT, and a second electrode end electrically connected to the high voltage-level input end; a sixth TFT including a gate electrically connected to the pull-down node, a first electrode end electrically connected to the output end, and a second electrode end electrically connected to the low voltage-level input end; and a pull-down capacitor electrically connected to the pull-down node and the low voltage-level input end; wherein the GOA circuit drives a pixel array by four of the GOA units, and the drive module comprises a pre-stage input diode electrically connected to the (n−1)th level input end and the circuit input end, and a post-stage input diode electrically connected to the (n+1)th level input end and the circuit input end.

2. The GOA circuit according to claim 1 , wherein the pull-up output module comprises: a seventh TFT including a gate electrically connected to the pull-up node, a first electrode end electrically connected to the second clock signal input end, and a second electrode end electrically connected to the output end; and a pill-up capacitor electrically connected to the pull-up node and the output end.

3. The GOA circuit according to claim 2 , wherein the first TFT to the seventh TFT are N type TFTs, and the GOA circuit is formed on an array substrate.

4. A gate driver on array (GOA) circuit, including a plurality of GOA units, each of the GOA units being provided with an (n−1)th level input end, an (n+1)th level input end, a first clock signal input end, a second clock signal input end, a high voltage-level input end, a low voltage-level input end, and a output end, and comprising: a drive module electrically connected to the (n−1)th level input end and the (n+4)th level input end; a pull-down module electrically connected to the drive module, the first clock signal input end, and the high voltage-level input end; a pull-down output module electrically connected to the first clock signal input end, the high voltage-level input end, the low voltage-level input end, and the output end, wherein the pull-down output module comprises a circuit input end electrically connected to the drive module and the pull-down module, and a pull-down node electrically connected to the pull-down module; and a pull-up output module electrically connected to the second clock signal input end and the output end, wherein the pull-up output module comprises a pull-up node electrically connected to the pull-down module; a first thin film transistor (TFT) including a gate electrically connected to the high voltage-level input end, a first electrode end electrically connected to the pull-up node of the pull-up output module, and a second electrode end electrically connected to the circuit input end of the pull-down output module; a second TFT including a gate electrically connected to the first clock signal input end, and a first electrode end electrically connected to the second electrode end of the first TFT; a third TFT including a first electrode end electrically connected to a second electrode end of the second TFT, and a second electrode end electrically connected to the pull-down node of the pull-down output module; a fourth TFT including a gate electrically connected to the circuit input end, and a first electrode end electrically connected to a gate of the third TFT; a fifth TFT including a gate electrically connected to a second electrode end of the fourth TFT, a first electrode end electrically connected to the first electrode end of the fourth TFT, and a second electrode end electrically connected to the high voltage-level input end; a sixth TFT including a gate electrically connected to the pull-down node, a first electrode end electrically connected to the output end, and a second electrode end electrically connected to the low voltage-level input end; and a pull-down capacitor electrically connected to the pull-down node and the low voltage-level input end.

5. The GOA circuit according to claim 4 , wherein the drive module comprises a pre-stage input diode electrically connected to the (n−1)th level input end and the circuit input end, and a post-stage input diode electrically connected to the (n+1)th level input end and the circuit input end.

6. The GOA circuit according to claim 4 , wherein the pull-up output module comprises: a seventh TFT including a gate electrically connected to the pull-up node, a first electrode end electrically connected to the second clock signal input end, and a second electrode end electrically connected to the output end; and a pull-up capacitor electrically connected t pull-up node and the output end.

7. The GOA circuit according to claim 6 , wherein the first ITT to the seventh ITT are N type TFTs, and the GOA circuit is formed on an array substrate.

8. The GOA circuit according to claim 4 , wherein the GOA circuit drives a pixel array by at least four of the GOA units.

9. The GOA circuit according to claim 8 , wherein the pixel array has two opposite sides electrically connected to four of the first GOA units which are cascaded and four of the second GOA units which are cascaded, respectively, and the first and second GOA units are controlled through four clock signals.

10. The GOA circuit according to claim 8 , wherein the pixel array has two opposite sides electrically connected to eight of the GOA units which are cascaded, and the GOA units are controlled through two clock signals.

11. A display device, comprising: an array substrate; and a gate driver on array (GO) circuit according to claim 4 formed on the array substrate.