9965439

Low Latency Multi-Protocol Retimers

PublishedMay 8, 2018
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
30 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. An apparatus for performing retiming between first and second devices according to a plurality of protocols, the apparatus comprising: a receiver operable to receive data; a transmitter to transmit data; a first data path coupled to the receiver and the transmitter and operable to transfer data received from the receiver to the transmitter during protocol specific training, the first data path comprising control circuitry to control protocol specific training of one or both of the transmitter and receiver in response to an indication of one protocol of the plurality of protocols; and a second data path coupled to the receiver and the transmitter, the second data path having a lower latency than the first data path and for use in transferring data received from the receiver to the transmitter after protocol specific training.

2

2. The apparatus defined in claim 1 wherein the protocol specific training comprises performing an equalization process.

3

3. The apparatus defined in claim 2 wherein the equalization process generates transmitter equalization coefficients to control equalization performed by the transmitter.

4

4. The apparatus defined in claim 1 wherein the second data path is used during common clock mode and the first data path is for use during non-common clock mode and during training.

5

5. The apparatus defined in claim 1 wherein a switch occurs from using the second data path to the first data path in response to receiving a predefined training set.

6

6. The apparatus defined in claim 1 further comprising a circuit to provide the indication in response to determining the physical layer (PHY) for transferring data from the receiver to the transmitter.

7

7. The apparatus defined in claim 6 wherein the circuit is operable to determine the PHY based on a strap option.

8

8. The apparatus defined in claim 6 wherein the circuit is operable to determine the PHY based on a sideband signal.

9

9. The apparatus defined in claim 6 wherein the circuit is operable to determine the PHY based on a training set modification.

10

10. The apparatus defined in claim 1 further comprising a multiplexer having a first input coupled to the first data path and a second input coupled to the second data path and an output coupled to the transmitter.

11

11. The apparatus defined in claim 1 wherein the first data path further comprises one or more link training state machines for the plurality of protocols, the one or more link training state machines being used by the control circuitry to perform link training according to the one protocol specified by the indication.

12

12. The apparatus defined in claim 11 wherein the control circuitry is operable to perform ordered set generation for link training associated with each of the plurality of protocols.

13

13. The apparatus defined in claim 1 wherein the first data path further comprises: a serial to parallel (S2P) converter coupled to convert first serial data received by the receiver to first parallel data; first logic coupled to the S2P converter to perform alignment, decoding and descrambling if necessary; an elastic buffer coupled to the first logic to store data after any alignment, decoding and descrambling; staging buffer circuitry coupled to the elastic buffer and the control circuitry, the staging buffer circuitry comprising a multiplexer responsive to one or more control signals to provide data from the elastic buffer or training data to the transmitter; and parallel to serial (P2S) converter coupled and operable to receive second parallel data from the staging buffer circuitry and convert the second parallel data to second serial data.

14

14. A method comprising: receiving data with a receiver of a multi-protocol retimer, where the data has been transferred according to one of a plurality of protocols; and transmitting data between the receiver and transmitter of the retimer using a first data path coupled to the receiver and the transmitter if transfer the data received by the receiver occurs during or before protocol specific training of one or both of the transmitter and receiver via control circuitry in response to an indication of one protocol of the plurality of protocols, or a second data path coupled to the receiver and the transmitter if transfer the data received by the receiver occurs after the protocol specific training, the second data path having a lower latency than the first data path.

15

15. The method defined in claim 14 wherein the protocol specific training includes comprises performing an equalization process.

16

16. The method defined in claim 15 wherein performing the equalization process comprises generating transmitter equalization coefficients to control equalization performed by the transmitter.

17

17. The method defined in claim 14 wherein the second data path is used during common clock mode and the first data path is for use during non-common clock mode and during protocol specific training.

18

18. The method defined in claim 14 further comprising switching from use of the second data path to the first data path in response to receiving a predefined training set.

19

19. The method defined in claim 14 further comprising providing the indication in response to determining the physical layer (PHY) type for transferring data from the receiver to the transmitter.

20

20. The method defined in claim 19 wherein determining the PHY type is based on a strap option.

21

21. The method defined in claim 19 wherein determining the PHY type is based on a sideband signal.

22

22. The method defined in claim 19 wherein determining the PHY is based on a training set modification.

23

23. The method defined in claim 14 further comprising selecting a control signal of a multiplexer having a first input coupled to the first data path and a second input coupled to the second data path to generate an output coupled to the transmitter.

24

24. The method defined in claim 14 further comprising running a link training state machine to perform link training according to the one protocol specified by the indication.

25

25. The method defined in claim 24 further comprising performing ordered set generation for the link training associated with one protocol.

26

26. The method defined in claim 14 further comprising: storing data in an elastic buffer during training; and controlling an output of a multiplexer coupled to the elastic buffer to output data, to the transmitter, from the elastic buffer or training data generated when performing the link training parallel to serial (P2S) converter coupled and operable to receive second parallel data from the staging buffer circuitry and convert the second parallel data to second serial data.

27

27. A system comprising: a pair of devices; a retimer coupled between the pair of devices to provide data flow in both directions between the pair of devices, wherein the data flow in each direction is performed by a receiver operable to receive data, a transmitter to transmit data, a first data path coupled to the receiver and the transmitter and operable to transfer data received from the receiver to the transmitter during protocol specific training, the first data path comprising control circuitry to control protocol specific training of one or both of the transmitter and receiver in response to an indication of one protocol of the plurality of protocols, and a second data path coupled to the receiver and the transmitter, the second data path having a lower latency than the first data path and for use in transferring data received from the receiver to the transmitter after protocol specific training.

28

28. The system defined in claim 27 wherein the protocol specific training includes comprises performing an equalization process.

29

29. The system defined in claim 28 wherein the equalization process generates transmitter equalization coefficients to control equalization performed by the transmitter.

30

30. The system defined in claim 27 wherein the second data path is used during common clock mode and the first data path is for use during non-common clock mode and during training.

Patent Metadata

Filing Date

Unknown

Publication Date

May 8, 2018

Inventors

Debendra Das Sharma

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Cite as: Patentable. “LOW LATENCY MULTI-PROTOCOL RETIMERS” (9965439). https://patentable.app/patents/9965439

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