Multicasting Computer Bus Switch

1. A switch for multicasting, the switch comprising: a first port providing a connection between the switch and a first end point; a second port providing a connection between the switch and a second end point; a buffer structured to receive and temporarily store data units having a destination address; a shared address space comprising: a first gross address portion associated with the first end point, wherein the first gross address portion comprises: a first individual portion unique to the first end point; and a first multicast portion used for a first multicast group that includes the first end point and the second end point; a second gross address portion associated with the second end point, wherein the second gross address portion comprises: a second individual portion unique to the second end point; and a second multicast portion used for a second multicast group that includes the second end point and at least one other end point; and logic that causes a first data unit having a first destination address in the first individual portion to be forwarded for transmission out the first port only and that causes a second data unit having a second destination address in the first multicast portion to be forwarded for transmission out of the first port and second port, wherein the second data unit is transmitted out of the first and second port by employing the logic to execute the following: causing the second data unit to be transmitted out of the first port; maintaining the second data unit in the buffer; replacing the second destination address of the second data unit with another address; and causing the second data unit with the another address to be transmitted out of the second port.

2. The switch of claim 1 , wherein the at least one other end point includes the first end point and a third end point.

3. The switch of claim 1 , wherein the at least one other end point includes a third end point and not the first end point.

4. The switch of claim 1 , wherein the another address is an address in the first multicast portion, and wherein the maintaining the second data unit in the buffer occurs after the second data unit has been transmitted out of the first port.

5. The switch of claim 1 , wherein the logic causes the first and second data units to be transmitted through the first port and the second port via a memory-mapped I/O into the shared memory address space.

6. The switch of claim 1 , wherein the first port and the second port are connected with a PCI Express communication bus, and wherein the first gross address portion is unique to the first end point and the second gross address portion is unique to the second end point.

7. The switch of claim 1 , wherein the first gross address portion further comprises a first broadcast portion used for a first broadcast group that includes all end points connected to the switch, wherein the first gross address portion and the second gross address portion do not overlap in the shared address space.

8. The switch of claim 7 , wherein the first individual portion, the first multicast portion, and the first broadcast portion do not overlap with one another.

9. The switch of claim 1 , wherein the shared address space is contiguous and wherein the first gross address space and second gross address space are contiguous.

10. The switch of claim 1 , wherein the first gross address portion has a first size, wherein the second gross address portion has a second size, and wherein the first size is equal to the second size.

11. A method of multicasting with a switch, the method comprising: connecting a first port of the switch with a first end point; connecting a second port of the switch with a second end point; structuring a buffer of the switch to receive and temporarily store data units having a destination address; providing a shared address space with a first gross address portion and a second gross address portion, wherein the first gross address portion is associated with the first end point and comprises a first individual portion unique to the first end point as well as a first multicast portion used for a first multicast group that includes the first end point and a second end point, wherein the second gross address portion is associated with the second end point and comprises a second individual portion unique to the second end point as well as a second multicast portion used for a second multicast group; utilizing logic of the switch to cause a first data unit having a first destination address in the first individual portion to be forwarded for transmission out of the first port only; utilizing the logic of the switch to cause a second data unit having a second destination address in the first multicast portion to be forwarded for transmission out of the first port and the second port; transmitting the second data unit out of the first port; storing the second data unit in the buffer; replacing the second destination address of the second data unit with another address; transmitting the second data unit with the another address out of the second port; and removing the second data unit from the buffer.

12. The method of claim 11 , wherein the second multicast group includes the second end point and at least one other end point.

13. The method of claim 11 , wherein the another address is an address in the first multicast portion, wherein the storing the second data unit in the buffer occurs after the transmitting the second data unit out of the first port, wherein the replacing the second destination address occurs while the second data unit is stored in the buffer, and wherein the removing the second data unit from the buffer occurs after the second data unit has been transmitted out of the second port.

14. The method of claim 11 , further comprising: employing a memory-mapped I/O to transmit the first and second data units through the first and second ports, respectively, into the shared memory address space.

15. The method of claim 11 , wherein the first port and second port are connected with a PCI Express communication bus.

16. The method of claim 11 , wherein the first gross address portion further comprises a first broadcast portion used for a first broadcast group that includes all end points connected to the switch.

17. The method of claim 16 , wherein the first broadcast portion does not overlap with the first multicast portion.

18. The method of claim 11 , wherein a size of the first gross address portion is variable.

19. A multicasting system, comprising: a buffer structured to receive and store data units having a destination address; a shared address space comprising: a first gross address portion associated with a first end point, wherein the first gross address portion comprises: a first individual portion unique to the first end point; and a first multicast portion used for a first multicast group that includes the first end point and a second end point; a second gross address portion associated with the second end point, wherein the second gross address portion comprises: a second individual portion unique to the second end point; and a second multicast portion used for a second multicast group that includes the second end point and at least one other end point; a first port connected with the first end point; a second port connected with the second end point; and logic that causes a first data unit having a first destination address in the first individual portion to be transmitted to the first end point only and that causes a second data unit having a second destination address in the first multicast portion to be transmitted to both the first end point and the second end point, wherein the second data unit is transmitted to both the first end point and the second end point by employing the logic to execute the following: causing the second data unit to be transmitted out of the first port; maintaining the second data unit in the buffer; replacing the second destination address of the second data unit with another address; causing the second data unit with the another address to be transmitted out of the second port.

20. The system of claim 19 , further comprising: a PCI Express communication bus in communication with both the first port and the second port, wherein the another address is an address in the first multicast portion, and wherein the maintaining the second data unit in the buffer occurs after the second data unit has been transmitted out of the first port.

21. A switch for multicasting, the switch comprising: a buffer structured to receive and temporarily store data units having a destination address; and a shared address space comprising: a first set of addresses assigned to a first gross address portion associated with a first end point, wherein the first set of addresses are sub-divided into addresses assigned to a first individual portion unique to the first endpoint and addresses assigned to a first multicast portion used for a first multicast group; and a second set of addresses assigned to a second gross address portion associated with a second end point, wherein the second set of addresses are sub-divided into addresses assigned to a second individual portion unique to the second endpoint and addresses assigned to a second multicast portion used for a second multicast group; a first port connected with the first end point; a second port connected with the second end point; and logic that causes a first data unit having a first destination address in the first individual portion to be forwarded for transmission out the first port only and that causes a second data unit having a second destination address in the first multicast portion to be forwarded for transmission out of the first port and second port, wherein the second data unit is transmitted out of the first and second port by employing the logic to execute the following: causing the second data unit to be transmitted out of the first port; maintaining the second data unit in the buffer; replacing the second destination address of the second data unit with another address; causing the second data unit with the another address to be transmitted out of the second port.

22. The switch of claim 21 , wherein the second set of addresses are adjacent to the first set of addresses in the shared address space, wherein the first gross address portion and the second gross address portion do not overlap.

23. The switch of claim 21 , wherein the second set of addresses are not adjacent to the first set of addresses in the shared address space, wherein the another address is an address in the first multicast portion, and wherein the maintaining the second data unit in the buffer occurs after the second data unit has been transmitted out of the first port.

24. The switch of claim 21 , wherein the addresses assigned to the first multicast portion are adjacent to the addresses assigned to the first individual portion.

25. The switch of claim 21 , wherein the addresses assigned to the first multicast portion are adjacent to the addresses assigned to the second multicast portion.

26. The switch of claim 21 , wherein the shared address space further comprises a third set of addresses assigned to a third gross address portion associated with a third end point, wherein the third set of addresses are sub-divided into addresses assigned to a third individual portion unique to the third endpoint and addresses assigned to a third multicast portion used for a third multicast group, and wherein the first gross address portion, the second gross address portion, and the third gross address portion do not overlap.