Memory Control Module and Control Method

1. A memory control module for controlling data access of a memory module, comprising: a storage unit for receiving and storing a target data to be stored in the memory module; an error correcting code (ECC) unit, coupled to the storage unit to receive the target data, comprising: a first Bose-Chaudhuri-Hocquenghem (BCH) code encoder, encoding the target data to generate a first set of BCH code parity check bits, wherein the first set of BCH code parity check bits has a first length; a second BCH code encoder, encoding the target data to generate a second set of BCH code parity check bits, wherein the second set of BCH code parity check bits has a second length different from the first length; and a Low Density Parity Check (LDPC) code encoder, coupled to the first BCH code encoder and the second BCH code encoder to receive the target data, the first set of BCH code parity check bits, and the second set of BCH code parity check bits from the first BCH code encoder and the second BCH code encoder, encoding the target data, the first set of BCH code parity check bits, and the second set of BCH code parity check bits to generate a set of LDPC code parity check bits; and a read/write control unit, coupled to the ECC unit, for converting the target data, the first set of BCH code parity check bits, the second set of BCH code parity check bits, and the set of LDPC code parity check bits into a data format of the memory module before writing the target data, the first set of BCH code parity check bits, the second set of BCH code parity check bits, and the set of LDPC code parity check bits into the memory module; wherein a total length of the first set of BCH code parity check bits and the second set of BCH code parity check bits is smaller than the length of the set of LDPC code parity check bits; wherein the read/write control unit generates a read data according to a content stored in the memory module and the read data comprises an intermediate data, the first set of BCH code parity check bits, the second set of BCH code parity check bits, and the set of LDPC code parity check bits, and the ECC unit further comprises: a first BCH code decoder for decoding the intermediate data according to the first set of BCH code parity check bits to correct an error bit in the intermediate data; a second BCH code decoder for decoding the intermediate data according to the second set of BCH code parity check bits to correct an error bit in the intermediate data; and an LDPC code decoder, coupled to the first BCH code decoder and the second BCH code decoder, for decoding the intermediate data according to the set of LDPC code parity check bits to correct an error bit in the intermediate data.

2. The memory control module of claim 1 , wherein the LDPC code decoder processes the intermediate data prior to the first BCH code decoder and the second BCH code decoder.

3. The memory control module of claim 1 , wherein the first BCH code decoder and the second BCH code decoder process the intermediate data prior to the LDPC code decoder.

4. The memory control module of claim 1 , further comprising: a control unit, coupled to the first BCH code decoder and the second BCH code decoder, for controlling a decoding sequence of the first BCH code decoder and the second BCH code decoder according to an order.

5. The memory control module of claim 4 , wherein the order is related to an order of code lengths of the first BCH code decoder and the second BCH code decoder.

6. The memory control module of claim 1 , wherein the total length of the first set of BCH code parity check bits, the second set of BCH code parity check bits, and the set of LDPC code parity check bits is smaller than or equal to the length of multiple parity check bits provided by the memory module.

7. The memory control module of claim 6 , wherein the memory module is a flash memory module.

8. A control method for controlling a memory module, comprising: receiving and storing a target data to be stored in the memory module; using a first Bose-Chaudhuri-Hocquenghem (BCH) code encoding method to encode the target data to generate a first set of BCH code parity check bits, wherein the first set of BCH code parity check bits has a first length; using a second BCH code encoding method to encode the target data to generate a second set of BCH code parity check bits, wherein the second set of BCH code parity check bits has a second length different from the first length; using a Low Density Parity Check (LDPC) code encoding method to encode the target data, the first set of BCH code parity check bits, and the second set of BCH code parity check bits to generate a set of LDPC code parity check bits; and converting the target data, the first set of BCH code parity check bits, the second set of BCH code parity check bits, and the set of LDPC code parity check bits into a data format of the memory module before writing the target data, the first set of BCH code parity check bits, the second set of BCH code parity check bits, and the set of LDPC code parity check bits into the memory module; wherein a total length of the first set of BCH code parity check bits and the second set of BCH code parity check bits is smaller than the length of the set of LDPC code parity check bits; wherein the method further comprises: generating a read data according to a content stored in the memory module, the read data comprising an intermediate data, the first set of BCH code parity check bits, the second set of BCH code parity check bits, and the set of LDPC code parity check bits; using a first BCH code decoding method to decode the intermediate data according to the first set of BCH code parity check bits to correct an error bit in the intermediate data; using a second BCH code decoding method to decode the intermediate data according to the second set of BCH code parity check bits to correct an error bit in the intermediate data; and using an LDPC code decoding method to decode the intermediate data according to the set of LDPC code parity check bits to correct an error bit in the intermediate data.

9. The method of claim 8 , wherein the first BCH code decoding method and the second BCH code decoding method process the intermediate data prior to the LDPC code decoding method.

10. The method of claim 8 , wherein the LDPC code decoding method processes the intermediate data prior to the first BCH code decoding method and the second BCH code decoding method.

11. The method of claim 8 further comprising: decoding the intermediate data by referring to the first set of BCH code parity check bits and the second set.

12. The method of claim 11 , wherein the order is related to a length order of the first set of BCH code parity check bits and the second set of BCH rode parity check bits.

13. The method of claim 8 , wherein the total length of the first set of BCH code parity check bits, the second set of BCH code parity check bits, and the set of LDPC code parity check bits is smaller than or equal to the length of multiple parity check bits provided by the memory module.

14. The method of claim 13 , wherein the memory module is a flash memory module.