Memory System

1. A device for use in a memory module coupled to a host memory controller over a bus, comprising: memory module controller, comprising hardware, to generate a request signal to the host memory controller indicating data is available in a buffer in the memory module to return as part of a read command sent from the host memory controller over the bus to the memory module for data stored in memory chips in the memory module, wherein the request signal has a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal is generated to indicate at least one of a first function, a second function and a third function function in addition to the request signal to the host memory controller, wherein the pulse width is generated as at least a first pulse width greater than the minimum pulse width to indicate the first function, as at least a second pulse width greater than the first pulse width to indicate the second function, and as at least a third pulse width greater than the second pulse width to indicate the third function.

2. The device of claim 1 , wherein the request signal causes the host memory controller to generate a grant signal, wherein the memory module controller further: sends data to the host memory controller in response to receiving the grant signal.

3. The device of claim 2 , wherein the pulse width causes the host memory controller to execute the at least one of the first function, the second function, and the third function indicated by the pulse width in addition to sending the grant signal in response to the request signal.

4. The device of claim 1 , wherein a pulse width equal to the minimum pulse width indicates only the request signal and no additional function.

5. The device of claim 1 , wherein the pulse width comprises one of a plurality of pulse widths equal to or multiples of the minimum pulse width, wherein the plurality of pulse widths are separated by a minimum number of clock cycles needed to guarantee detection of the pulse width by the host memory controller, and wherein the pulse widths encode different functions in the request signal.

6. The device of claim 5 , wherein the minimum pulse width comprises 2 clocks and wherein generating the request signal with the pulse width of one of a plurality of pulse widths of 6, 10 and 14 clocks indicates a different function for the host memory controller to perform in addition to a processing of the request signal.

7. The device of claim 1 , wherein the request signal comprise a clock enable signal.

8. A device coupled to at least one memory module over a bus, comprising: host memory controller, comprising hardware, to: send a read command over the bus to the memory module for data stored in memory chips in the memory module; detect a request signal from the memory module indicating that data is available in a buffer in the memory module to return as part of the read command, wherein the request signal has a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal indicates at least one of a first function, a second function and a third function in addition to the request signal to the host memory controller, wherein only the first function is indicated when the request signal is generated having a first pulse width greater than the minimum pulse width, wherein the second function is indicated when the request signal is generated having a second pulse width greater than the first pulse width, and wherein the third function is indicated when the request signal is generated having a third pulse width greater than the second pulse width; determine whether the pulse width of the request signal indicates at least one of the first function, the second function or the third function in response to the pulse width comprising one of the first pulse width, the second pulse width, and the third pulse width; and execute the at least one of the first function, the second function, and the third function indicated in the pulse width.

9. The device of claim 8 , wherein the host memory controller further: generates a grant signal to send to the memory module over the bus in response to receiving the request signal.

10. The device of claim 8 , wherein the host memory controller further: determines the pulse width to be equal to the minimum pulse width, wherein the pulse width comprises the request signal without an additional of the first, second or third function in response to the pulse width of the request signal being equal to the minimum pulse width.

11. A method performed in a memory module coupled to a host memory controller over a bus, comprising: generating a request signal to the host memory controller indicating data is available in a buffer in the memory module to return as part of a read command sent from the host memory controller over the bus to the memory module for data stored in memory chips in the memory module, wherein the request signal has a pulse width greater than or equal to a minimum pulse width wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal is generated to indicate at least one of a first function, a second function and a third function in addition to the request signal to the host memory controller, wherein the pulse width is generated as a first pulse width greater than the minimum pulse width to indicate the first function, as a second pulse width greater than the first pulse width to indicate the second function, and as a third pulse width greater than the second pulse width to indicate the third function.

12. The method of claim 11 , wherein the request signal causes the host memory controller to generate a grant signal, further comprising: sending data to the host memory controller in response to receiving the grant signal.

13. The method of claim 12 , wherein the pulse width causes the host memory controller to execute the at least one of the first function, the second function, and the third function indicated by the pulse width in addition to sending the grant signal in response to the request signal.

14. The method of claim 11 , wherein a pulse width equal to the minimum pulse width indicates only the request signal and no additional of the first, second or third function.

15. The method of claim 11 , wherein the pulse width comprises one of a plurality of pulse widths equal to or multiples of the minimum pulse width, wherein the plurality of pulse widths are separated by a minimum number of clock cycles needed to guarantee detection of the pulse width by the host memory controller, and wherein the pulse widths encode different functions in the request signal.

16. A method for communicating, by a host memory controller, with at least one memory module over a bus, comprising: sending a read command over the bus to the memory module for data stored in memory chips in the memory module; detecting a request signal from the memory module indicating that data is available in a buffer in the memory module to return as part of the read command, wherein the request signal has a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the request signal is detected, and wherein the pulse width of the request signal indicates at least one of a first function, a second function and a third function in addition to the request signal, wherein only the first function is indicated when the request signal is generated having a first pulse width greater than the minimum pulse width, wherein the second function is indicated when the request signal is generated having a second pulse width greater than the first pulse width, and wherein the third function is indicated when the request signal is generated having a third pulse width greater than the second pulse width; determining whether the pulse width of the request signal indicates at least one of the first function, the second function or the third function in response to the pulse width comprising one of the first pulse width, the second pulse width, and the third pulse width; and executing the at least one of the first function, the second function, and the third function indicated in the pulse width.

17. The method of claim 16 , further comprising: generating a grant signal to send to the memory module over the bus in response to receiving the request signal.

18. The method of claim 16 , further comprising: determining the pulse width to be equal to the minimum pulse width, wherein the pulse width comprises the request signal without an additional of the first, second or third function in response to the pulse width of the request signal being equal to the minimum pulse width.