Shift Register Unit and Driving Method Thereof, Scan Driving Circuit and Display Device

1. A shift register unit, comprising an input terminal, an output terminal, a reset terminal and a first noise leak terminal, the shift register unit further comprising: an input module connected to the input terminal and a first node, and configured to pull up a voltage at the first node under control of a signal received at the input terminal; an output module connected to the output terminal and the first node, and configured to pull up a voltage at the output terminal by using a first clock signal under control of the voltage at the first node; a reset module connected to the reset terminal and the first node, and configured to pull down the voltage at the first node under control of a signal received at the reset terminal; an output pull-down module connected to the output terminal, and configured to pull down the voltage at the output terminal under control of a second clock signal; and a first noise leak module connected to the first noise leak terminal and the first node, and configured to release a noise voltage at the first node to the first noise leak terminal under control of a third clock signal; wherein the first noise leak module is further configured to disconnect an electrical connection between the first noise leak terminal and the first node during a time period in which the voltage at the first node is pulled up; the shift register unit further comprises: a second noise leak terminal; and a second noise leak module connected to the second noise leak terminal, the first node and a clock signal terminal and configured to release a noise voltage at the first node to the second noise leak terminal under control of a fourth clock signal received at the clock signal terminal.

2. The shift register unit according to claim 1 , wherein the first noise leak module comprises a first transistor, a gate of the first transistor being connected to the third clock signal, one of a source and a drain of the first transistor being connected to the first noise leak terminal, and the other of the source of and the drain of the first transistor being connected to the first node; and during at least a part of the time period in which the voltage at the first node is pulled up, a voltage of a signal received at the first noise leak terminal is greater than or equal to a voltage of the third clock signal.

3. The shift register unit according to claim 1 , wherein the second noise leak module is further configured to disconnect an electrical connection between the second noise leak terminal and the first node during a time period in which the voltage at the first node is pulled up.

4. The shift register unit according to claim 3 , wherein the second noise leak module comprises a second transistor, a gate of the second transistor being connected to the fourth clock signal, one of a source and a drain of the second transistor being connected to the second noise leak terminal, and the other of the source and the drain of the second transistor being connected to the first node; and during at least a part of the time period in which the voltage at the first node is pulled up, a voltage of a signal received at the second noise leak terminal is greater than or equal to a voltage of the fourth clock signal.

5. The shift register unit according to claim 4 , wherein phases of the third clock signal, the first clock signal, the fourth clock signal and the second clock signal lag sequentially within a single clock cycle of the shift register unit.

6. The shift register unit according to claim 1 , wherein the output module comprises: a first capacitor, a first terminal thereof being connected to the first node; and a third transistor, a gate thereof being connected to the first node, one of a source and a drain thereof being connected to the first clock signal, and the other of the source and the drain thereof being connected to the output terminal.

7. The shift register unit according to claim 1 , wherein the output pull-down module comprises a fourth transistor, a gate of the fourth transistor being connected to the second clock signal, one of a source and a drain of the fourth transistor being connected to the output terminal, and the other of the source and the drain of the fourth transistor being connected to a low level voltage line.

8. The shift register unit according to claim 1 , wherein the input module comprises a fifth transistor, a gate of the fifth transistor being connected to the input terminal, one of a source and a drain of the fifth transistor being connected to a high level voltage line, and the other of the source and the drain of the fifth transistor being connected to the first node.

9. The shift register unit according to claim 1 , wherein the reset module comprises a sixth transistor, a gate of the sixth transistor being connected to the reset terminal, one of a source and a drain of the sixth transistor being connected to the first node, and the other of the source and the drain of the sixth transistor being connected to a low level voltage line.

10. A driving method for a shift register unit, wherein the shift register unit comprises an input terminal, an output terminal, a reset terminal, a first noise leak terminal, a second noise leak terminal, and a first node located inside the shift register unit, the driving method comprises: pulling up a voltage at the first node under control of a signal received at the input terminal; pulling up a voltage at the output terminal by using a first clock signal under control of a voltage at the first node, and disconnecting an electrical connection between the first noise leak terminal and the first node during a time period in which the voltage at the first node is pulled up; pulling down the voltage at the first node under control a signal received at the reset terminal, and pulling down the voltage at the output terminal under control of a second clock signal; releasing a noise voltage at the first node to the first noise leak terminal under control of a third clock signal; and releasing the noise voltage at the first node to the second noise leak terminal under control of a fourth clock signal.

11. A scan driving circuit comprising multiple stages of shift register units, wherein the shift register unit comprises: an input terminal; an output terminal; a reset terminal; a first noise leak terminal; an input module connected to the input terminal and a first node, and configured to pull up a voltage at the first node under control of a signal received at the input terminal; an output module connected to the output terminal and the first node, and configured to pull up a voltage at the output terminal by using a first clock signal under control of the voltage at the first node; a reset module connected to the reset terminal and the first node, and configured to pull down the voltage at the first node under control of a signal received at the reset terminal; an output pull-down module connected to the output terminal, and configured to pull down the voltage at the output terminal under control of a second clock signal; and a first noise leak module connected to the first noise leak terminal and the first node, and configured to release a noise voltage at the first node to the first noise leak terminal under control of a third clock signal, and further configured to disconnect an electrical connection between the first noise leak terminal and the first node during a time period in which the voltage at the first node is pulled up; wherein an input terminal of the shift register unit at an N-th stage is connected to an output terminal of the shift register unit at an (N−2)-th stage, a first noise leak terminal of the shift register unit at the N-th stage is connected to an output terminal of the shift register unit at the (N−1)-th stage, and a reset terminal of the shift register unit at the N-th stage is connected to an output terminal of the shift register unit at the (N+2)-th stage, the N being greater than or equal to 3; the shift register unit further comprises: a second noise leak terminal; and a second noise leak module connected to the second noise leak terminal, the first node and a clock signal terminal and configured to release a noise voltage at the first node to the second noise leak terminal under control of a fourth clock signal received at the clock signal terminal.

12. The scan driving circuit according to claim 11 , wherein the second noise leak terminal of the shift register unit at the N-th stage is connected to an output terminal of the shift register unit at the (N+1)-th stage.

13. A display device comprising a scan driving circuit according to claim 11 .

14. The shift register unit according to claim 2 , wherein the output module comprises: a first capacitor, a first terminal thereof being connected to the first node; and a third transistor, a gate thereof being connected to the first node, one of a source and a drain thereof being connected to the first clock signal, and the other of the source and the drain thereof being connected to the output terminal.

15. The shift register unit according to claim 2 , wherein the output pull-down module comprises a fourth transistor, a gate of the fourth transistor being connected to the second clock signal, one of a source and a drain of the fourth transistor being connected to the output terminal, and the other of the source and the drain of the fourth transistor being connected to a low level voltage line.

16. The shift register unit according to claim 2 , wherein the input module comprises a fifth transistor, a gate of the fifth transistor being connected to the input terminal, one of a source and a drain of the fifth transistor being connected to a high level voltage line, and the other of the source and the drain of the fifth transistor being connected to the first node.

17. The shift register unit according to claim 2 , wherein the reset module comprises a sixth transistor, a gate of the sixth transistor being connected to the reset terminal, one of a source and a drain of the sixth transistor being connected to the first node, and the other of the source and the drain of the sixth transistor being connected to a low level voltage line.

18. The scan driving circuit according to claim 11 , wherein the first noise leak module comprises a first transistor, a gate of the first transistor being connected to the third clock signal, one of a source and a drain of the first transistor being connected to the first noise leak terminal, and the other of the source of and the drain of the first transistor being connected to the first node; and during at least a part of the time period in which the voltage at the first node is pulled up, a voltage of a signal received at the first noise leak terminal is greater than or equal to a voltage of the third clock signal.

19. The scan driving circuit according to claim 18 , wherein the second noise leak terminal of the shift register unit at the N-th stage is connected to an output terminal of the shift register unit at the (N+1)-th stage.

20. The display device according to claim 13 , wherein the second noise leak terminal of the shift register unit at the N-th stage is connected to an output terminal of the shift register unit at the (N+1)-th stage.