Method and Device for Controlling Memory

1. A memory controller comprising: a dirty group detector configured to, in response to receiving a request for writing data to a memory, modify addresses of a cache group related to a physical address of the memory using a plurality of hash functions, the cache group including a plurality of cache sets, increase a plurality of counters, each of the plurality of counters corresponding to an address of the modified addresses of the cache group, and detect whether the cache group is in a dirty state based on the counters;, and a dirty list manager configured to manage the cache group in the dirty state and a dirty list comprising dirty bits according to a result of the detecting;, wherein each of the dirty bits indicate indicates whether a one of the plurality of cache sets set included in the cache group is in the dirty state, and wherein the dirty group detector is further configured to reduce the counters by half in response to the result of the detecting being that the cache group is in the dirty state.

2. The memory controller of claim 1, wherein the dirty group detector is further configured to detect that the cache group is in the dirty state in response to all of the counters corresponding to the modified addresses of the cache group being equal to or greater than a threshold.

3. The memory controller of claim 2, wherein the dirty group detector is further configured to reduce the counters by half in response to the result of the detecting being that the cache group is in the dirty state.

4. The memory controller of claim 1, wherein each of the cache sets comprises a single tag area and a single data area.

5. The memory controller of claim 1, wherein the dirty list manager is further configured to, in response to receiving the request for writing data to the memory, determine whether the cache group is in the dirty state by determining whether addresses of the cache group are included in the dirty list.

6. The memory controller of claim 5, wherein the dirty list manager is further configured to, in response to the addresses of the cache group not being included in the dirty list, delete an address of another cache group in the dirty list and manage the dirty list.

7. The memory controller of claim 6, wherein the dirty list manager is further configured to, in response to a cache set in the dirty state being included in the deleted cache group, output an address of the cache set in the dirty state included in the deleted cache group.

8. A computing device comprising: a core; a cache configured to store partial information in a memory in a cache set comprising a single tag area and a single data area; and a memory controller configured to, in response to receiving a request for the memory from the core, track whether the cache is in a dirty state, predict whether the cache is hit, wherein the cache hit indicates that the cache includes data associated with the request, and transmit the request to the memory or the cache based on a result of the tracking or a result of the predicting;, wherein the memory controller comprises: a tracker configured to, in response to receiving a request for the memory from the core, modify addresses of a cache group related to a physical address of the memory, the cache group including a plurality of cache sets, increase a plurality of counters, each of the plurality of counters corresponding to an address of the modified addresses of the cache group, detect whether the cache group is in a dirty state based on the counters, and track a dirty state of the cache by managing a dirty list comprising the cache group in the dirty state and dirty bits according to a result of the detecting;, wherein the tracker reduces the counters by half in response to a detection that the cache group is in the dirty state, a predictor configured to predict whether the cache is hit;, and a memory interface configured to transmit the request to the memory or the cache based on the result of the tracking or the result of the predicting;, wherein each of the dirty bits indicate indicates whether one of the plurality of the cache set in the cache group sets is in the dirty state.

9. The computing device of claim 8, wherein the tracker is further configured to, in response to receiving a request for the memory, determine whether the cache group is in the dirty state by determining whether addresses of the cache group are included in the dirty list; and the memory interface is further configured to, in response to the request being a request for reading first data in the memory, the tracker determining that the cache group is in a clean state, and the predictor predicting that a cache in the cache group is a cache hit, transmit a request for reading data to the memory or the cache based on a utilization rate of a bandwidth of the memory or the cache.

10. The computing device of claim 8, wherein the memory interface is further configured to, in response to the request being a request for reading first data in the memory, the tracker determining that the cache group is in a clean state, and the predictor predicting that a cache in the cache group is a cache miss, transmit the first data to the cache after transmitting the request for reading data to the memory.

11. The computing device of claim 8, wherein the memory controller is further configured to, in response to the request being a request for writing second data in the memory, transmit the second data to the cache in response to the tracker determining that the cache group is in the dirty state, and transmit the second data to the cache and the memory in response to the tracker determining that the cache group is in a clean state.

12. The computing device of claim 8, wherein the memory is located outside the package; and the predictor is an instruction-based predictor.

13. A method of controlling a memory, the method comprising: in response to receiving a request for a memory, modifying addresses of a cache group related to a physical address of the memory using a plurality of hash functions, the cache group including a plurality of cache sets, increasing a plurality of counters, each of the plurality of counters corresponding to an address of the modified addresses of the cache group, and detecting whether the cache group is in a dirty state based on the counters; ;reducing the counters by half in response to detecting that the cache group is in the dirty state, and managing the cache group in the dirty state and a dirty list comprising dirty bits according to a result of the detecting;, wherein each of the dirty bits indicate indicates whether a one of the plurality of cache set in the cache group sets is in the dirty state.

14. The method of claim 13, wherein the detecting comprises: detecting that the cache group is in the dirty state in response to all of the counters corresponding to the modified addresses of the cache group being equal to or greater than a threshold.

15. The method of claim 14, further comprising reducing the counters by half in response to detecting that the cache group is in the dirty state.

16. The method of claim 13, wherein each of the cache sets comprises a single tag area and a single data area.

17. The method of claim 13, further comprising determining whether the cache group is in the dirty state by determining whether addresses of the cache group are included in the dirty list in response to receiving a request for writing data to the memory.

18. The method of claim 17, further comprising deleting an address of another cache group included in the dirty list in response to the addresses of the cache group not being included in the dirty list.

19. The method of claim 18, further comprising outputting an address of a cache set in the dirty state included in the deleted cache group in response to the cache set in the dirty state being included in the deleted cache group.