According to one embodiment, a semiconductor wafer includes a substrate, an AlN buffer layer, a foundation layer, a first high Ga composition layer, a high Al composition layer, a low Al composition layer, an intermediate unit and a second high Ga composition layer. The first layer is provided on the foundation layer. The high Al composition layer is provided on the first layer. The low Al composition layer is provided on the high Al composition layer. The intermediate unit is provided on the low Al composition layer. The second layer is provided on the intermediate unit. The first layer has a first tensile strain and the second layer has a second tensile strain larger than the first tensile strain. Alternatively, the first layer has a first compressive strain and the second layer has a second compressive strain smaller than the first compressive strain.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor wafer, comprising: a substrate having a first surface; an AlN buffer layer provided on the first surface of the substrate; a first layer provided on the AlN buffer layer, the first layer comprising a first nitride semiconductor comprising Al and Ga; a second layer provided on the first layer, the second layer comprising a second nitride semiconductor comprising Ga; a third layer provided on the second layer, the third layer comprising a third nitride semiconductor comprising Al and Ga, a Ga composition ratio in the third layer being lower than a Ga composition ratio in the second layer; a fourth layer provided directly on the third layer, the fourth layer comprising a fourth semiconductor comprising Al and Ga, a Ga composition ratio in the fourth layer being lower than the Ga composition ratio in the second layer, an Al composition ratio in the fourth layer being lower than an Al composition ratio in the third layer; an intermediate unit provided on the fourth layer, the intermediate unit comprising one element selected from the group consisting of Si, Mg, and B, a thickness of the intermediate unit being not less than a 0.2 atom layer and not more than 3 nanometers; and a fifth layer provided on the intermediate unit, the fifth layer having a composition same as a composition of the second layer, the fifth layer having a tensile strain, and the second layer having a compressive strain.
2. The semiconductor wafer according to claim 1 , wherein a coefficient of thermal expansion of the substrate is less than a coefficient of thermal expansion of the second nitride semiconductor.
3. The semiconductor wafer according to claim 1 , wherein the third layer receives a tensile strain, and the third layer has a first lattice spacing along a first axis parallel to the first surface, a difference between the first lattice spacing and a second lattice spacing is not less than 0.6% and not more than 1.4% of the second lattice spacing, the second lattice spacing is a lattice spacing of an unstrained nitride semiconductor having a composition same as a composition of the third layer.
4. The semiconductor wafer according to claim 1 , wherein a concentration of an impurity of at least one of an acceptor and a donor in the third layer is not more than 1×10 18 cm −3 , and a concentration of an impurity of at least one of an acceptor and a donor in the fourth layer is not more than 1×10 18 cm −3 .
5. The semiconductor wafer according to claim 1 , wherein a thickness of the intermediate unit is thinner than a thickness of the third layer.
6. The semiconductor wafer according to claim 1 , wherein the intermediate unit is provided in an island configuration.
7. The semiconductor wafer according to claim 1 , wherein the intermediate unit includes one selected from SiN, MgN, and BN.
8. The semiconductor wafer according to claim 1 , wherein an Al composition ratio to group III elements in the fourth layer is not less than 0.2 and not more than 0.8.
9. The semiconductor wafer according to claim 1 , wherein a thickness of the second layer is not less than 100 nanometers and not more than 5 micrometers.
10. The semiconductor wafer according to claim 1 , wherein a thickness of the fifth layer is not less than 100 nanometers and not more than 5 micrometers.
11. The semiconductor wafer according to claim 1 , wherein the substrate is one selected from a Si substrate, a SiC substrate, a GaP substrate, and an InP substrate.
12. The semiconductor wafer according to claim 1 , wherein a dislocation density in the fifth layer is not more than 2×10 9 /cm 2 .
13. The semiconductor device according to claim 1 , wherein the intermediate unit includes multiple openings.
14. A semiconductor device comprising: a substrate having a first surface; an AlN buffer layer of AlN, the AlN buffer layer being provided on the first surface of the substrate; a first layer provided on the AlN buffer layer, the first layer comprising a first nitride semiconductor comprising Al and Ga; a second layer provided on the first layer, the second layer comprising a second nitride semiconductor comprising Ga; a third layer provided on the second layer, the third layer comprising a third nitride semiconductor comprising Al, a Ga composition ratio in the third layer being lower than a Ga composition ratio in the second layer; a fourth layer provided directly on the third layer, the fourth layer comprising a fourth semiconductor comprising Al and Ga, a Ga composition ratio in the fourth layer being lower than the Ga composition ratio in the second layer, an Al composition ratio in the fourth layer being lower than an Al composition ratio in the third layer; an intermediate unit provided on the fourth layer, the intermediate unit comprising one selected from Si, Mg, and B, a thickness of the intermediate unit being not less than a 0.2 atom layer and not more than 3 nanometers; a fifth layer provided on the intermediate unit, the fifth layer having a composition same as a composition of the second layer; and a functional layer provided on fifth layer, the fifth layer having a tensile strain, and the second layer having a compressive strain.
15. The semiconductor device according to claim 14 , wherein a coefficient of thermal expansion of the substrate is less than a coefficient of thermal expansion of the fifth nitride semiconductor.
16. The semiconductor device according to claim 14 , wherein the intermediate unit includes one selected from SiN, MgN, and BN.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 23, 2015
June 26, 2018
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