A hybrid PCB system has a hybrid redistribution layer that redistributes a large pad-to-pad pitch to a smaller, finer pad-to-pad pitch and applies hybrid materials to balance the thermal-mechanical stress. The hybrid PCB system combines wafer level packaging, IC substrate and high density PCB technologies within a single hybrid PCB. The hybrid PCB system addresses the opportunity for interconnect reliability, design and assembly of a electronic components with pad pitches less than 400 microns directly to a PCB without need of an IC substrate or interposer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A printed circuit board comprising: a. an inner core structure comprising a laminated stack of a plurality of non-conductive layers and a plurality of conductive layers, wherein the plurality of non-conductive layers have a first coefficient of thermal expansion value and a first elastic modulus value; b. a buffer layer laminated to the inner core structure, wherein the buffer layer comprises a first dielectric material having a second coefficient of thermal expansion value less than the first coefficient of thermal expansion value, further wherein the buffer layer has a second elastic modulus value; c. an intermediate conductive layer coupled to the buffer layer; d. an outer layer coupled to the intermediate conductive layer and the buffer layer, wherein the outer layer comprises a second dielectric material having a third coefficient of expansion value less than the second coefficient of thermal expansion value, further wherein the outer layer has a third elastic modulus value, wherein the second elastic modulus value is less than the first elastic modulus value and the second elastic modulus value is less than the third elastic modulus value; and e. an outer conductive layer coupled to the outer layer.
2. The printed circuit board of claim 1 wherein the plurality of conductive layers includes an inner core structure outer surface conductive layer, and the intermediate conductive layer is coupled to the inner core structure outer surface conductive layer by one or more first conductive microvias.
3. The printed circuit board of claim 2 wherein the outer conductive layer is coupled to the intermediate conductive layer by one or more second conductive microvias.
4. The printed circuit board of claim 3 wherein the inner core structure outer surface includes a plurality of inner core structure circuit features each having corresponding inner core structure circuit feature dimensions, wherein each of the plurality of the inner core structure circuit features comprise one of a first contact pad diameter, a first trace transmission line width or a first via end diameter.
5. The printed circuit board of claim 4 wherein the outer conductive layer includes a plurality of outer layer circuit features each having corresponding outer surface circuit feature dimensions, wherein each of the plurality of the outer layer circuit features comprise one of a second contact pad diameter, a second trace transmission line width or a second via end diameter.
6. The printed circuit board of claim 5 wherein the outer surface circuit feature dimensions are smaller than the inner core structure circuit feature dimensions.
7. The printed circuit board of claim 1 wherein the buffer layer comprises a plurality of different materials blended together, each of the different materials having a different coefficient of thermal expansion value, and the buffer layer has a second composite coefficient of thermal expansion value.
8. The printed circuit board of claim 1 wherein the outer layer comprises a plurality of different materials blended together, each of the different materials having a different coefficient of thermal expansion value, and the outer layer has a third composite coefficient of thermal expansion value.
9. The printed circuit board of claim 1 wherein the buffer layer comprises a plurality of first dielectric material layers each separated by a conductive layer.
10. The printed circuit board of claim 9 wherein the conductive layers separating each of the plurality of first dielectric material layers are selectively interconnected by a plurality of conductive micovias.
11. The printed circuit board of claim 1 wherein the outer layer comprises a plurality of second dielectric material layers each separated by a conductive layer.
12. The printed circuit board of claim 11 wherein the conductive layers separating each of the plurality of second dielectric material layers are selectively interconnected by a plurality of conductive micovias.
13. The printed circuit board of claim 1 wherein the intermediate conductive layer is applied to the buffer layer and the outer conductive layer is coupled to the outer layer using one of a semi-additive process, an advanced modified semi-additive process or fully additive process.
14. The printed circuit board of claim 1 wherein the inner core structure is fabricated using standard printed circuit board processes and the buffer layer, the intermediate conductive layer, the outer layer and the outer conductive layer are fabricated using integrated circuit substrate processes.
15. A printed circuit board comprising: a. an inner core structure comprising a laminated stack of a plurality of non-conductive layers and a plurality of conductive layers including an inner core structure outer surface conductive layer, wherein the inner core structure outer surface includes a plurality of inner core structure circuit features each having corresponding inner core structure circuit feature dimensions, further wherein each of the plurality of the inner core structure circuit features comprise one of a first contact pad diameter, a first trace transmission line width, or a first via end diameter, wherein the plurality of non-conductive layers have a first coefficient of thermal expansion value; b. an outer layer coupled to the inner core structure, wherein the outer layer comprises a dielectric material having a second coefficient of expansion value less than the first coefficient of thermal expansion value; and c. an outer conductive layer coupled to the outer layer, wherein the outer conductive layer includes a plurality of outer layer circuit features each having corresponding outer surface circuit feature dimensions, further wherein each of the plurality of the outer layer circuit features comprise one of a second contact pad diameter, a second trace transmission line width, or a second via end diameter, wherein the outer surface circuit feature dimensions are smaller than the inner core structure circuit feature dimensions.
16. The printed circuit board of claim 15 wherein the plurality of non-conductive layers have a first elastic modulus value and the outer layer has a second elastic modulus value, further wherein the second elastic modulus value is less than the first elastic modulus value.
17. The printed circuit board of claim 15 wherein the outer conductive layer is coupled to the inner core structure outer surface conductive layer by one or more conductive microvias.
18. The printed circuit board of claim 15 wherein the outer layer comprises a plurality of different materials blended together, each of the different materials having a different coefficient of thermal expansion value, and the outer layer has a second composite coefficient of thermal expansion value.
19. The printed circuit board of claim 15 wherein the outer layer comprises a plurality of second dielectric material layers each separated by a conductive layer.
20. The printed circuit board of claim 19 wherein the conductive layers separating each of the plurality of second dielectric material layers are selectively interconnected by a plurality of conductive micovias.
21. The printed circuit board of claim 15 wherein the outer conductive layer is coupled to the outer layer using one of a semi-additive process, an advanced modified semi-additive process or fully additive process.
22. The printed circuit board of claim 15 wherein the inner core structure is fabricated using standard printed circuit board processes and the outer layer and the outer conductive layer are fabricated using integrated circuit substrate processes.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 2, 2016
June 26, 2018
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