A semiconductor device includes a clock shifting circuit suitable for shifting a write pulse which is synchronized with a clock, in response to write latency signals, and generating shifting pulses and a mask write read signal; and a flag generation circuit suitable for generating a mask write flag by latching a mask write command or outputting the mask write command as the mask write flag, in response to the shifting pulses.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a clock shifting circuit configured for shifting a write pulse which is synchronized with a clock, based on write latency signals, and generating shifting pulses; and a flag generation circuit configured for generating a mask write flag by latching a mask write command or outputting the mask write command as the mask write flag, based on the shifting pulses.
2. The semiconductor device according to claim 1 , wherein the write latency signals include a first write latency signal and a second write latency signal, the second write latency signal is enabled in a first period, and the first period is set as a period in which a write latency is equal to or greater than a first predetermined value.
3. The semiconductor device according to claim 2 , wherein the shifting pulses include a first shifting pulse and a second shifting pulse, and the clock shifting circuit generates both the first shifting pulse and the second shifting pulse in the first period.
4. The semiconductor device according to claim 1 , wherein the write latency signals include a first write latency signal and a second write latency signal, the first write latency signal is enabled in a second period, and the second period is set as a period in which a write latency is less than a first predetermined value and is equal to or greater than a second predetermined value.
5. The semiconductor device according to claim 4 , wherein the shifting pulses include a first shifting pulse and a second shifting pulse, and the clock shifting circuit generates the second shifting pulse in the second period.
6. The semiconductor device according to claim 1 , wherein the write latency signals include a first write latency signal and a second write latency signal, both the first and second write latency signals are disabled in a third period, and the third period is set as a period in which a write latency is less than a second predetermined value.
7. The semiconductor device according to claim 6 , wherein the clock shifting circuit blocks generation of the shifting pulses in the third period.
8. The semiconductor device according to claim 1 , wherein the shifting pulses include a first shifting pulse and a second shifting pulse, and wherein the flag generation circuit comprises: a first latch configured for latching the mask write command in synchronization with the first shifting pulse, and outputting an output signal; and a second latch configured for latching the output signal of the first latch in synchronization with the second shifting pulse, and outputting an output signal.
9. The semiconductor device according to claim 8 , wherein the flag generation circuit further comprises: a first selector configured for transferring the output signal of the first latch to the second latch or transferring the mask write command to the second latch, based on a first select control signal; a second selector configured for outputting the output signal of the second latch or outputting the mask write command, based on a second select control signal; and a third selector configured for outputting an output signal of the second selector as the mask write flag or outputting the mask write command as the mask write flag, based on a delay select signal.
10. The semiconductor device according to claim 9 , wherein, in a period in which a write latency is equal to or greater than a first predetermined value, the first selector transfers the output signal of the first latch to the second latch, the second selector selects and outputs the output signal of the second latch, and the third selector outputs the output signal of the second selector as the mask write flag.
11. The semiconductor device according to claim 9 , wherein, in a period in which a write latency is less than the first predetermined value and is equal to or greater than a second predetermined value, the first selector transfers the mask write command to the second latch, the second selector selects and outputs the output signal of the second latch, and the third selector outputs the output signal of the second selector as the mask write flag.
12. The semiconductor device according to claim 9 , wherein, in a period in which a write latency is less than the second predetermined value, the third selector outputs the mask write command as the mask write flag.
13. The semiconductor device according to claim 1 , further comprising: a mask read control circuit configured for generating a mask read control signal from the write pulse and a mask write read signal based on the mask write flag and the delay select signal, wherein the clock shifting circuit is configured for shifting the write pulse which is synchronized with the clock, based on the write latency signals, and generating the mask write read signal.
14. The semiconductor device according to claim 13 , wherein the mask read control circuit comprises: a signal synthesizer configured for synthesizing the write pulse and the mask write flag and generating a synthesized write pulse; and a selective output configured for outputting the synthesized write pulse or the mask write read signal based on the delay select signal.
15. The semiconductor device according to claim 14 , wherein the mask read control circuit generates the mask read control signal from the mask write read signal in a first period and a second period, generates the mask read control signal from the write pulse in a third period, the first period is set as a period in which a write latency is equal to or greater than a first predetermined value, the second period is set as a period in which a write latency is less than the first period and is equal to or greater than a second predetermined value, and the third period is set as a period in which a write latency is less than the second predetermined value.
16. A semiconductor device comprising: a first latch configured for latching a mask write command in synchronization with a first shifting pulse, and outputting an output signal; a second latch configured for latching the output signal of the first latch in synchronization with a second shifting pulse, and outputting an output signal; a first selector configured for transferring the output signal of the first latch to the second latch or transferring the mask write command to the second latch, based on a first select control signal; a second selector configured for outputting the output signal of the second latch or outputting the mask write command, based on a second select control signal; and a third selector configured for outputting an output signal of the second selector as a mask write flag or outputting the mask write command as the mask write flag, based on a delay select signal.
17. The semiconductor device according to claim 16 , wherein the first shifting pulse is generated in a first period, the second shifting pulse is generated in the first period and a second period, the first period is set as a period in which a write latency is equal to or greater than a first predetermined value, and the second period is set as a period in which a write latency is less than the first predetermined value and is equal to or greater than a second predetermined value.
18. The semiconductor device according to claim 16 , wherein, in a period in which a write latency is equal to or greater than a first predetermined value, the first selector transfers the output signal of the first latch to the second latch, the second selector selects and outputs the output signal of the second latch, and the third selector outputs the output signal of the second selector as the mask write flag.
19. The semiconductor device according to claim 16 , wherein, in a period in which a write latency is less than a first predetermined value and is equal to or greater than a second predetermined value, the first selector transfers the mask write command to the second latch, the second selector selects and outputs the output signal of the second latch, and the third selector outputs the output signal of the second selector as the mask write flag.
20. The semiconductor device according to claim 16 , wherein, in a period in which a write latency is less than a second predetermined value, the third selector outputs the mask write command as the mask write flag.
21. The semiconductor device according to claim 16 , further comprising: a mask read control circuit configured for generating a mask read control signal from a write pulse and a mask write read signal based on the mask write flag and the delay select signal.
22. The semiconductor device according to claim 21 , wherein the mask read control circuit comprises: a signal synthesizer configured for synthesizing the write pulse and the mask write flag and generating a synthesized write pulse; and a selective output configured for outputting the synthesized write pulse or the mask write read signal based on the delay select signal.
23. The semiconductor device according to claim 21 , wherein the mask read control circuit generates the mask read control signal from the mask write read signal in a first period and a second period, generates the mask read control signal from the write pulse in a third period, the first period is set as a period in which a write latency is equal to or greater than a first predetermined value, the second period is set as a period in which a write latency is less than the first period and is equal to or greater than a second predetermined value, and the third period is set as a period in which a write latency is less than the second predetermined value.
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July 18, 2017
July 17, 2018
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