A method of fabricating a semiconductor structure includes forming first and second features in a scribe region of a semiconductor substrate in which the first and second features are electrically isolated from each other; forming an interlayer dielectric layer over the first and second features; and forming a first contact in the interlayer dielectric layer and connected to the first feature and a second contact in the interlayer dielectric layer and connected to the second feature.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating a semiconductor structure, the method comprising: forming first and second features in a scribe region of a semiconductor substrate, wherein the first and second features are electrically isolated from each other; forming an interlayer dielectric layer over the first and second features; and forming in the interlayer dielectric layer a first contact connected to the first feature, a second contact connected to the second feature, a third contact connected to the first feature, and a fourth contact connected to the second feature.
2. The method of claim 1 , wherein the forming the first and second features comprises: forming an isolation structure in the semiconductor substrate as the second feature, wherein the isolation structure defines an active region as the first feature.
3. The method of claim 1 , further comprising: forming a conductive line connecting the first contact and the third contact.
4. The method of claim 1 , further comprising: forming a gate structure at least on the first feature and between the first and third contacts.
5. The method of claim 1 , further comprising: forming a conductive line connecting the second contact and the fourth contact.
6. The method of claim 1 , wherein the forming the first and second features comprises: forming an isolation structure in the semiconductor substrate to separate a first active region and a second active region, wherein the first active region is the first feature; and forming a dielectric layer over the second active region as the second feature.
7. The method of claim 1 , wherein the forming the first and second features comprises: doping a first dopant into the semiconductor substrate to form a first active region as the first feature; and doping a second dopant into the semiconductor substrate to form a second active region as the second feature, wherein the first dopant and the second dopant are different.
8. A method of fabricating a semiconductor structure, the method comprising: forming first and second features on a semiconductor substrate, wherein the first and second features are electrically isolated from each other; forming an interlayer dielectric layer over the first and second features; forming in the interlayer dielectric layer a first contact connected to the first feature and a second contact connected to the second feature; and detecting if a short circuit occurs between the first contact and the second contact, wherein the detecting comprises: applying a first voltage to the first contact; applying a second voltage to the second contact, wherein the first voltage is different from the second voltage; and detecting if a current occurs between the first contact and the second contact.
9. The method of claim 8 , further comprising: forming a first conductive line connected to the first contact.
10. The method of claim 8 , further comprising: forming a second conductive line connected to the second contact.
11. The method of claim 8 , wherein the first and second features are formed in a scribe region between first and second dies on the semiconductor substrate.
12. A semiconductor structure, comprising: a semiconductor substrate comprising a scribe region; a first feature in the scribe region; a second feature in the scribe region, wherein the first feature and the second feature are electrically isolated from each other; a first contact and a gate structure on the first feature; a second contact on the second feature; a third contact on the first feature, wherein the gate structure is between the first contact and the third contact; and a conductive line connecting the first contact and the third contact.
13. The semiconductor structure of claim 12 , wherein the first feature is an active region.
14. The semiconductor structure of claim 12 , wherein the second feature comprises a dielectric material.
15. The semiconductor structure of claim 12 , wherein the first feature is an n-type doped region, and the second feature is a p-type doped region.
16. The method of claim 1 , wherein forming the second feature comprises forming an isolation structure such that a top surface of the isolation structure is lower than a top surface of the first feature.
17. The method of claim 8 , further comprising forming a third contact and a gate structure between the first and third contacts.
18. The method of claim 8 , further comprising: forming an isolation structure in the semiconductor substrate as the second feature; and forming an active region in the semiconductor substrate as the first feature.
19. The method of claim 8 , further comprising: doping the first feature with a first dopant to form a first active region; and doping the second feature with a second dopant to form a second active region.
20. The method of claim 8 , wherein forming the second feature comprises forming an isolation structure such that a top surface of the isolation structure is lower than a top surface of the first feature.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 5, 2017
July 31, 2018
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.