An object of the disclosure is to provide cancelling of the output voltage deviation in a switching converter, caused by Equivalent Series Inductance (ESL) of the output capacitor, using switching node information. A further object of the disclosure is to eliminate a step-like voltage deviation in the equalized output, further eliminating the need to increase the Panic comparator offset reference, and eliminating the need to reduce the bandwidth of the pulse-width modulation control loop. Still further, another object of the disclosure is to merge some of the new components depending on the circuit topology. Still further, another object of the disclosure is to implement the new components with the same silicon as the control block, for matching the output voltage ripple and the cancelling signal control.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A switching converter, comprising: an output stage, configured to provide an output stage output voltage at an inductor, wherein said inductor is connected to an output capacitor at an output of said switching converter; and a control block, configured to control said output stage based on a control input and a reference; a logic gate, configured to invert said output stage output voltage, and configured to generate a signal swing proportional to said output stage output voltage; a voltage divider, configured to attenuate an output voltage of said logic gate, and configured to generate a cancelling signal; and an adder, configured to add said cancelling signal to a converter output voltage of said switching converter, to generate a control signal input.
2. The circuit of claim 1 , wherein said voltage divider is resistive or capacitive.
3. The circuit of claim 1 , wherein said output capacitor comprises a parasitic resistance and a parasitic inductance, wherein said parasitic resistance and said parasitic inductance generate a voltage ripple on said converter output voltage.
4. The circuit of claim 1 , wherein said cancelling signal is configured to eliminate a step-like voltage deviation in said converter output voltage.
5. The circuit of claim 1 , wherein said voltage divider comprises a first resistor and a capacitor connected between said logic gate output and said adder, and a second resistor connected between said converter output voltage and said adder.
6. The circuit of claim 5 , wherein a ratio of said second resistor and said first resistor is configured to be a ratio of said parasitic inductance and said inductor.
7. The circuit of claim 5 , wherein said capacitor is configured to be smaller than said output capacitor, and a product of said first resistor and said capacitor is larger than a switching period.
8. The circuit of claim 1 , wherein said control block comprises a pulse-width modulation control loop, configured to supply said control signal input to said control block.
9. The circuit of claim 1 , wherein said control block comprises an error amplifier configured to receive said control signal input, and configured to supply an input to said pulse-width modulation control loop.
10. The circuit of claim 1 , wherein said control block comprises a panic comparator configured to receive said control signal input, and configured to supply said reference to said control block.
11. The circuit of claim 1 , wherein said output stage comprises an inverter, a high side device, and a low side device.
12. The circuit of claim 11 , wherein said high side device is PMOS and said low side device is NMOS.
13. The circuit of claim 1 , wherein said panic comparator comprises a transconductance amplifier, configured to receive said converter output voltage, a current comparator, further comprising a current source and an inverter, and a high pass amplifier, further comprising a first current source and a second current source, a first device and a second device, an input capacitor connected between said converter output voltage and a gate of said first device, and a resistor connected between said gate of said first device, a gate of said second device, and a drain of said first device.
14. The circuit of claim 13 , wherein a cancelling capacitor is configured to said logic gate output and is configured to provide an input to said panic comparator at said gate of said first device.
15. The circuit of claim 13 , wherein a ratio of said cancelling capacitor and said input capacitor is configured to be a ratio of said parasitic inductance and said inductor.
16. The circuit of claim 13 , wherein said transconductance amplifier is configured to convert a voltage difference into a current signal, and configured to supply said current signal to said inverter of said current comparator.
17. The circuit of claim 16 , wherein said high pass amplifier is configured to generate a sum of an output signal with said current signal of said transconductance amplifier.
18. The circuit of claim 17 , wherein said current comparator is configured to compare said current source to said sum of said output signal of said high pass amplifier and said current signal of said transconductance amplifier.
19. The circuit of claim 1 , wherein said switching converter comprises a Buck switching converter.
20. The circuit of claim 1 , wherein said switching converter comprises a Boost switching converter.
21. The circuit of claim 1 , wherein said switching converter comprises a Buck-Boost switching converter.
22. The circuit of claim 1 , wherein said switching converter comprises a multi-phase (N-phase) Buck switching converter.
23. The circuit of claim 1 , wherein said switching converter comprises a hysteretic type converter.
24. A method for a switching converter control circuit robust to robust to Equivalent Series Inductance (ESL), comprising the steps of: providing a switching converter, comprising an output stage and a control block; generating a signal swing proportional to an output stage output voltage, by inverting said output stage output voltage with a logic gate; attenuating an output voltage of said logic gate, to generate a cancelling signal; and adding said cancelling signal to a converter output voltage, to generate a control signal input.
25. The method of claim 24 , wherein a pulse-width modulation control loop supplies an input to said control block.
26. The method of claim 24 , wherein a parasitic resistance and a parasitic inductance generate a voltage ripple on said converter output voltage.
27. The method of claim 24 , wherein a voltage divider attenuates said output voltage of said logic gate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 28, 2017
August 7, 2018
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