Techniques described herein generally include methods and systems related to cooperatively caching data in a chip multiprocessor. Cooperatively caching of data in the chip multiprocessor is managed based on an eviction rate of data blocks from private caches associated with each individual processor core in the chip multiprocessor. The eviction rate of data blocks from each private cache in the cooperative caching system is monitored and used to determine an aggregate eviction rate for all private caches. When the aggregate eviction rate exceeds a predetermined value, for example the threshold beyond which network flooding can occur, the cooperative caching system for the chip multiprocessor is disabled, thereby avoiding network flooding of the chip multiprocessor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method to control caching of data in a chip multiprocessor having a plurality of processor cores, the method comprising: monitoring, by the chip multiprocessor, an eviction rate of a first private cache that is operated and used by a first processor core of the chip multiprocessor; monitoring, by the chip multiprocessor, an eviction rate of a second private cache that is operated and used by a second processor core of the chip multiprocessor; computing, by the chip multiprocessor, an aggregate eviction rate based on the monitored eviction rate of the first private cache and the monitored eviction rate of the second private cache; detecting, by the chip multiprocessor, that the aggregate eviction rate has exceeded a particular threshold; and in response to the detection, disabling, by the chip multiprocessor, cooperative caching for the chip multiprocessor.
2. The method of claim 1 , wherein disabling the cooperative caching for the chip multiprocessor comprises partially disabling the cooperative caching for the chip multiprocessor.
3. The method of claim 2 , wherein partially disabling the cooperative caching for the chip multiprocessor comprises halting replication of one or more data blocks stored in the first private cache or the second private cache.
4. The method of claim 1 , wherein disabling the cooperative caching for the chip multiprocessor comprises completely disabling the cooperative caching for the chip multiprocessor.
5. The method of claim 4 , wherein completely disabling the cooperative caching for the chip multiprocessor comprises preventing cross storage of one or more data blocks between the first processor core and the second processor core.
6. The method of claim 5 , wherein preventing the cross storage of the one or more data blocks between the first processor core and the second processor core comprises at least one of: preventing one or more data blocks used by the first processor core from being stored in the second private cache; and preventing one or more data blocks used by the second processor core from being stored in the first private cache.
7. The method of claim 5 , wherein preventing the cross storage of the one or more data blocks between the first processor core and the second processor core comprises designating each data block stored in the first private cache and the second private cache as a unique data block.
8. The method of claim 1 , wherein disabling the cooperative caching for the chip multiprocessor comprises disabling the cooperative caching for a particular time interval.
9. The method of claim 1 , wherein disabling the cooperative caching for the chip multiprocessor comprises disabling the cooperative caching until a particular number of operations are performed by the chip multiprocessor.
10. The method of claim 1 , wherein detecting that the aggregate eviction rate has exceeded the particular threshold comprises detecting that the aggregate eviction rate has exceeded a first threshold.
11. The method of claim 10 , wherein in response to the detection that the aggregate eviction rate has exceeded the first threshold, halting replication of one or more data blocks stored in the first private cache or the second private cache.
12. The method of claim 10 , wherein detecting that the aggregate eviction rate has exceeded the particular threshold comprises detecting that the aggregate eviction rate has exceeded a second threshold, wherein the second threshold is higher than the first threshold.
13. The method of claim 12 , wherein in response to the detection that the aggregate eviction rate has exceeded the second threshold, preventing cross storage of one or more data blocks between the first processor core and the second processor core.
14. The method of claim 1 , wherein monitoring the eviction rate of the first private cache comprises counting evictions from an eviction counter associated with the first private cache, and wherein monitoring the eviction rate of the second private cache comprises counting evictions from an eviction counter associated with the second private cache.
15. The method of claim 1 , wherein computing the aggregate eviction rate comprises measuring a number of evictions performed over a time period from private caches that are disposed on the chip multiprocessor.
16. The method of claim 15 , wherein computing the aggregate eviction rate further comprises polling an eviction register of each private cache for which the number of evictions performed therefrom over the time period is measured.
17. A chip multiprocessor formed on a single die, the chip multiprocessor comprising: a first processor core; a first private cache that is operated and used by the first processor core; a second processor core; a second private cache that is operated and used by the second processor core; a first eviction counter that corresponds to the first private cache; a second eviction counter that corresponds to the second private cache; and a cache coherence engine coupled to the first private cache and the second private cache, wherein the cache coherence engine is configured to: control cross storage of data blocks between the first processor core and the second processor core based on an aggregation of data polled from the first eviction counter and the second eviction counter.
18. The chip multiprocessor of claim 17 , wherein the cache coherence engine is configured to control the cross storage of the data blocks between the first processor core and the second processor core by control of storage of data blocks used by the first processor core in the second private cache, and by control of storage of data blocks used by the second processor core in the first private cache.
19. The chip multiprocessor of claim 17 , wherein the cache coherence engine is configured to control the cross storage of the data blocks between the first processor core and the second processor core based on an eviction rate of the data blocks from the first private cache and the second private cache, and wherein the eviction rate is determined by the aggregation of data polled from the first eviction counter and the second eviction counter.
20. A non-transitory computer-readable medium including instructions that, in response to execution by a chip multiprocessor, cause the chip multiprocessor to perform or cause to be performed: monitor an eviction rate of a first private cache that is operated and used by a first processor core of the chip multiprocessor; monitor an eviction rate of a second private cache that is operated and used by a second processor core of the chip multiprocessor; compute an aggregate eviction rate based on the monitored eviction rate of the first private cache and the monitored eviction rate of the second private cache; detect that the aggregate eviction rate has exceeded a particular threshold; and in response to the detection, disable cooperative caching for the chip multiprocessor.
21. The non-transitory computer-readable medium of claim 20 , wherein to compute the aggregate eviction rate, the instructions, in response to execution by the chip multiprocessor, cause the chip multiprocessor to perform or cause to be performed: measure a number of evictions performed over a time period from private caches that are disposed on the chip multiprocessor.
22. The non-transitory computer-readable medium of claim 21 , wherein to disable the cooperative caching for the chip multiprocessor, the instructions, in response to execution by the chip multiprocessor, cause the chip multiprocessor to perfoim or cause to be performed: halt a replication engine from replication of one or more data blocks stored in the first private cache or the second private cache, in response to the detection that the aggregate eviction rate has exceeded a first threshold; and prevent cross storage of the one or more data blocks between the first processor core and the second processor core, in response to the detection that the aggregate eviction rate has exceeded a second threshold, wherein the second threshold is larger than the first threshold.
23. The non-transitory computer-readable medium of claim 20 , wherein to disable the cooperative caching for the chip multiprocessor, the instructions, in response to execution by the chip multiprocessor, cause the chip multiprocessor to perform or cause to be performed: disable the cooperative caching for a particular time interval.
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March 5, 2017
August 14, 2018
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