A semiconductor device and a method for fabricating the semiconductor device are provided. In the method for fabricating the semiconductor device, at first, a FinFET (Field-Effect Transistor) device is provided. Then, spacers and various mask layers are formed on gate structures of the FinFET device to provide a self-alignment structure. Thereafter, source/drain contacts and gate contacts are formed in the self-alignment structure to enable the source/drain contacts to be electrically connected to the source/drain structures of the FinFET device, and enable the gate contacts to be electrically connected to the gate structures. Therefore, self-alignment is achieved.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for fabricating a semiconductor device, the method comprising: providing a plurality of gate structures formed on a semiconductor substrate; forming a plurality of first mask layers on the gate structures; forming a second mask layer on the first mask layers and the gate structures; forming a plurality of first openings in the second mask layer, wherein a plurality of remained portions of the second mask layer are located on the gate structures; filling the first openings with a plurality of third mask layers; removing the remained portions of the second mask layer to expose the first mask layers; forming a plurality of fourth mask layers on the exposed first mask layers; removing the third mask layers to form a plurality of second openings; filling the second openings with a plurality of first conductive layers; forming a fifth mask layer on the first conductive layers and the fourth mask layers; forming a plurality of third openings in the fifth mask layer, wherein the third openings are located on the first conductive layers and the gate structures; and forming a plurality of second conductive layers in the third openings to enable the second conductive layers to be electrically connected to the first conductive layers and the gate structures.
2. The method of claim 1 , wherein providing the gate structures formed on the semiconductor substrate comprises: providing the semiconductor substrate; forming a plurality of dummy gate structures on the semiconductor substrate, wherein each of the dummy gate structures comprises a main portion and a spacer enclosing the main portion; etching the dummy gate structures to remove the main portion of each of the dummy gate structures and form a plurality of etched spacers defining fourth openings; and filling the fourth openings with a dielectric material and a conductive material to form the gate structures.
3. The method of claim 2 , wherein providing the gate structures formed on the semiconductor substrate further comprises polishing the gate structures to decrease a height of each of the gate structures.
4. The method of claim 1 , wherein the second openings includes a plurality of lower portions located between the gate structures.
5. The method of claim 1 , wherein a material of the second mask layer is different from a material of the third mask layer.
6. The method of claim 5 , wherein the second mask layer is spin-on carbon (SOC).
7. The method of claim 5 , wherein the third mask layer is silicon.
8. The method of claim 1 , wherein the gate structures are high-k metal gates structures.
9. The method of claim 1 , wherein the second conductive layers are metal.
10. The method of claim 1 , wherein each of the gate structures is provided to have a height substantially in a range from 10 nm (nanometer) to 32 nm.
11. A method for fabricating a transistor device, the method comprising: providing a FinFET (Fin Field-Effect Transistor) device, wherein the FinFET device comprises: a semiconductor substrate; a plurality of fin structures located on the semiconductor substrate; a plurality of source/drain structures located on the fin structures; and a plurality of gate structures located on the fin structures; forming a plurality of first mask layers on the gate structures; forming a second mask layer on the first mask layers, the gate structures and the source/drain structures; forming a plurality of first openings in the second mask layer, wherein a plurality of remained portions of the second mask layer are located on the gate structures in forming the first openings; filling the first openings with a plurality of third mask layers; removing the remained portions of the second mask layer to expose the first mask layers; forming a plurality of fourth mask layers on the exposed first mask layers; removing the third mask layers to form a plurality of second openings corresponding to the source/drain structures; filling the second openings with a plurality of first conductive layers to enable the source/drain structures to be electrically connected to the first conductive layers; forming a fifth mask layer on the first conductive layers and the fourth mask layers; forming a plurality of source/drain openings and gate openings in the fifth mask layer, wherein the source/drain openings are located on the first conductive layers, and the gate openings are located on the gate structures; forming a plurality of source/drain contacts in the source/drain openings to enable the source/drain contacts to be electrically connected to the first conductive layers; and forming a plurality of gate contacts in the gate openings to enable the gate contacts to be electrically connected to the gate structures.
12. The method of claim 11 , wherein providing the FinFET device comprises: providing the semiconductor substrate; forming the fin structures, the source/drain structures and a plurality of dummy gate structures on the semiconductor substrate, wherein each of the dummy gate structures comprises a main portion and a spacer enclosing the main portion; etching the dummy gate structures to remove the main portion of each of the dummy gate structures and form a plurality of etched spacers defining fifth openings; and filling the fifth openings with a dielectric material and a conductive material to form the gate structures.
13. The method of claim 12 , wherein providing the gate structures formed on the semiconductor substrate further comprises polishing the gate structures to decrease a height of each of the gate structures.
14. The method of claim 11 , wherein the second openings includes a plurality of lower portions located between the gate structures.
15. The method of claim 11 , wherein a material of the second mask layer is different from a material of the third mask layer.
16. The method of claim 15 , wherein the second mask layer is spin-on carbon (SOC).
17. The method of claim 15 , wherein the third mask layer is silicon.
18. The method of claim 11 , wherein the gate structures are high-k metal gates structures.
19. The method of claim 11 , wherein the source/drain contacts and the gate contacts are metal.
20. The method of claim 11 , wherein each of the gate structures has a height substantially in a range from 10 nm (nanometer) to 32 nm.
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May 3, 2017
August 14, 2018
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