A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method to manufacture a complementary metal-oxide-semiconductor (CMOS) transistor, comprising: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an n-type metal-oxide-semiconductor (NMOS) transistor area; forming a second gate electrode pattern on the gate insulating film in a p-type metal-oxide-semiconductor (PMOS) transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern in the PMOS transistor area; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type lightly doped drain (LDD) region in the PMOS transistor area using the first photoresist pattern, wherein the performing of the first ion injection process comprises performing ion injection through the exposed second gate electrode pattern in the PMOS transistor area; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern in the NMOS transistor area; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region in the NMOS transistor area using the second photoresist pattern, wherein the performing of the second ion injection process comprises performing ion injection through the exposed first gate electrode pattern in the NMOS transistor area; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
2. The method of claim 1 , further comprising forming separation films before the forming of the gate insulating film.
3. The method of claim 2 , wherein the performing of the first ion injection process further comprises: performing ion injection such that the n-type well region is formed deeper than the separation films, and such that a depth of the n-type well region below the second gate electrode pattern is shallower than a depth of the n-type well region below the separation films.
4. The method of claim 2 , wherein the performing of the second ion injection process further comprises: performing ion injection such that the p-type well region is formed deeper than the separation films, and such that a depth of the p-type well region below the first gate electrode pattern is shallower than a depth of the p-type well region below the separation films.
5. The method of claim 1 , wherein the performing of the first ion injection process further comprises either one or both of: performing an n-type ion injection process to form an n-type threshold voltage adjustment area below the second gate electrode pattern in the PMOS transistor area; and performing an n-type ion injection process to form an n-type Halo region in the PMOS transistor area.
6. The method of claim 1 , wherein the performing of the second ion injection process further comprises either one or both of: performing a p-type ion injection process to form a p-type threshold voltage adjustment area below the first gate electrode pattern in the NMOS transistor area; and performing a p-type ion injection process to form a p-type Halo region in the NMOS transistor area.
7. The method of claim 1 , further comprising: forming a third photoresist pattern covering the PMOS transistor area; and performing a high concentration n-type ion injection process into the NMOS transistor area to form an n-type source region and an n-type drain region.
8. The method of claim 7 , further comprising: removing the third photoresist pattern; forming a fourth photoresist pattern covering the NMOS transistor area; and performing a high concentration p-type ion injection process into the PMOS transistor area to form a p-type source region and a p-type drain region.
9. A method to manufacture a complementary metal-oxide-semiconductor (CMOS) transistor, comprising: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an n-type metal-oxide-semiconductor (NMOS) transistor area; forming a second gate electrode pattern on the gate insulating film in a p-type metal-oxide-semiconductor (PMOS) transistor area; forming a first photoresist pattern covering the first gate electrode pattern and portions of the semiconductor substrate that are exposed on sides of the first gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type lightly doped drain (LDD) region using the first photoresist pattern, wherein the performing of the first ion injection process comprises performing ion injection through the second gate electrode pattern; removing the first photoresist pattern; forming a second photoresist pattern covering the second gate electrode pattern and portions of the semiconductor substrate exposed on sides of the second gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region using the second photoresist pattern, wherein the performing of the second ion injection process comprises performing ion injection through the first gate electrode pattern; and removing the second photoresist pattern.
10. The method of claim 9 , wherein the performing of the first ion injection process further comprises: forming an n-type threshold voltage adjustment area in an upper portion of the n-type well region, at a surface of the semiconductor substrate below the gate insulating film.
11. The method of claim 9 , wherein the performing of the second ion injection process further comprises: forming a p-type threshold voltage adjustment area in an upper portion of the p-type well region, at a surface of the semiconductor substrate below the gate insulating film.
12. The method of claim 9 , further comprising: forming separation films in the semiconductor substrate before the forming of the gate insulating film, wherein the performing of the first ion injection process further comprises performing ion injection such that the n-type well region is formed deeper than the separation films, and such that a depth of the n-type well region below the second gate electrode pattern is shallower than a depth of the n-type well region below the separation films, and wherein the performing of the second injection process further comprises performing ion injection such that the p-type well region is formed deeper than the separation films, and such that a depth of the p-type well region below the first gate electrode pattern is shallower than a depth of the p-type well region below the separation films.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 23, 2016
August 28, 2018
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.