A transition frequency multiplier semiconductor device having a first source region, a second source region, and a common drain region is disclosed. A first channel region is located between the first source region and the common drain region, and a second channel region is located between the second source region and the common drain region. A first gate region is located within the first channel region to control current flow between the first source region and the common drain region, while a second gate region is located within the second channel region to control current flow between the second source region and the common drain region. An inactive channel region is located between the first channel region and the second channel region such that the first channel region is electrically isolated from the second channel region. A conductive interconnect couples the first source region to the second gate region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A transition frequency multiplier semiconductor device comprising: a first source region; a second source region; a common drain region; a first channel region located between the first source region and the common drain region; a second channel region located between the second source region and the common drain region; a first gate region located within the first channel region to control current flow between the first source region and the common drain region; a second gate region located within the second channel region to control current flow between the second source region and the common drain region; an inactive channel region located between the first channel region and the second channel region such that the first channel region is electrically isolated from the second channel region; and a conductive interconnect coupled between the first source region and the second gate region.
2. The transition frequency multiplier semiconductor device of claim 1 wherein the first channel region and the second channel region are substantially equal in width.
3. The transition frequency multiplier semiconductor device of claim 1 wherein a first width of the first channel and a second width of the second channel are substantially unequal.
4. The transition frequency multiplier semiconductor device of claim 3 wherein the second channel width is at least twice that of the first channel width.
5. The transition frequency multiplier semiconductor device of claim 1 further including at least one additional gate region that extends continuously across both the first channel region and the second channel region.
6. The transition frequency multiplier semiconductor device of claim 1 further including at least one additional gate region that extends across the first channel region and at least one other additional gate region that extends across the second channel region, wherein the at least one additional gate region and the at least one other additional gate region are separated by the inactive channel region.
7. The transition frequency multiplier semiconductor device of claim 1 further including an additional gate region that extends across the second channel region adjacent to and parallel with the second gate region, and wherein the first channel region has no additional gate region that is adjacent to and parallel with the first gate region.
8. The transition frequency multiplier semiconductor device of claim 1 wherein the inactive channel region is an ion implantation damaged region.
9. The transition frequency multiplier semiconductor device of claim 1 wherein the inactive channel region is a mesa etched region.
10. The transition frequency multiplier semiconductor device of claim 1 further comprising: an RF ground region; and an un-gated channel region between the first source region, the second source region and the RF ground region.
11. The transition frequency multiplier semiconductor device of claim 10 further including a first resistor coupled between the first source region and the RF ground region.
12. The transition frequency multiplier semiconductor device of claim 11 wherein the first resistor is a bulk resistor made up of selective ion implantation damage.
13. The transition frequency multiplier semiconductor device of claim 11 wherein the first resistor is a thin film resistor.
14. The transistor frequency multiplier semiconductor device of claim 11 further including a second resistor coupled between the second source region and the RF ground region.
15. The transition frequency multiplier semiconductor device of claim 14 wherein the second resistor is a bulk resistor made up of selective ion damage.
16. The transition frequency multiplier semiconductor device of claim 14 wherein the second resistor is a thin film resistor.
17. The transition frequency multiplier semiconductor device of claim 14 further including a third source region, a third gate region coupled to the second source region and a third resistor coupled between the third source region and the RF ground region.
18. A transition frequency multiplier semiconductor device comprising: a first source region; a second source region; a common drain region; a first channel region located between the first source region and the common drain region; a second channel region located between the second source region and the common drain region; a first gate region located within the first channel region to control current flow between the first source region and the common drain region; a second gate region located within the second channel region to control current flow between the second source region and the common drain region; at least one additional gate region that extends across the first channel region and at least one other additional gate region that extends across the second channel region; an inactive channel region located between the first channel region and the second channel region such that the first channel region is electrically isolated from the second channel region; and a conductive interconnect coupled between the first source region and the second gate region.
19. The transition frequency multiplier semiconductor device of claim 18 wherein a first width of the first channel and a second width of the second channel are substantially unequal.
20. A transition frequency multiplier array comprising: a plurality of transition frequency multiplier semiconductor devices that each comprise: a first source region; a second source region; a common drain region; a first channel region located between the first source region and the common drain region; a second channel region located between the second source region and the common drain region; a first gate region located within the first channel region to control current flow between the first source region and the common drain region; a second gate region located within the second channel region to control current flow between the second source region and the common drain region; at least one additional gate region that extends across the first channel region and at least one other additional gate region that extends across the second channel region; an inactive channel region located between the first channel region and the second channel region such that the first channel region is electrically isolated from the second channel region; a conductive interconnect coupled between the first source region and the second gate region; an RF ground region; and an un-gated channel region between the first source region, the second source region and the RF ground region, wherein adjacent ones of the plurality of transition frequency multiplier semiconductor devices are coupled together by adjacent ones of the RF ground region.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 3, 2016
August 28, 2018
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.