Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a centerline between the semiconductor dice and operably coupled with integrated circuitry of the first and second semiconductor dice. Another group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the first semiconductor die. A further group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the second semiconductor die. Methods of forming semiconductor device packages include aligning first and second semiconductor dice with active surfaces facing each other, the first and second semiconductor dice each including bond pads along a centerline thereof and additional bond pads laterally offset from the centerline thereof.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a semiconductor device package, the method comprising: securing a back side of a first semiconductor die to a substrate, the first semiconductor die comprising a first bond pad over an active surface and located and centered on a centerline thereof, a second bond pad over the active surface and laterally offset from the centerline thereof, and an electrically isolated region over the active surface and laterally offset from the centerline thereof, the centerline of the first semiconductor die defined substantially midway between and parallel to opposing lateral edges of the active surface; aligning a second semiconductor die with the first semiconductor die with an active surface of the second semiconductor die facing the active surface of the first semiconductor die, the second semiconductor die comprising a third bond pad over the active surface and located and centered on a centerline thereof, a fourth bond pad over the active surface and laterally offset from the centerline thereof, and an electrically isolated region over the active surface and laterally offset from the centerline thereof, the centerline of the second semiconductor die defined substantially midway between and parallel to opposing lateral edges of the active surface, the aligning comprising: substantially aligning the first and third bond pads along respective centerlines of the first and second semiconductor dice with each other; substantially aligning the second bond pad of the first semiconductor die and the electrically isolated region of the second semiconductor die with each other on a first side of the respective centerlines of the first and second semiconductor dice; and substantially aligning the fourth bond pad of the second semiconductor die and the electrically isolated region of the first semiconductor die with each other on a second side of the respective centerlines of the first and second semiconductor dice opposite the first side; and physically and electrically coupling the first bond pad along the centerline of the first semiconductor die with the third bond pad along the centerline of the second semiconductor die using conductive elements.
2. The method of claim 1 , further comprising: forming each of the first and the second semiconductor dice, comprising: forming the first and third bond pads over the active surface and located and centered on the respective centerlines of the first and second semiconductor dice; and forming the second and fourth bond pads over the active surface and laterally offset from the respective centerlines of the first and second semiconductor dice.
3. The method of claim 2 , wherein: forming each of the first and the second semiconductor dice further comprises forming dummy bond pads over the active surface and laterally offset from the respective centerlines of the first and second semiconductor dice, the dummy bond pads electrically isolated from integrated circuitry of the respective first and second semiconductor dice; substantially aligning the second bond pad and the electrically isolated region of the second semiconductor die with each other comprises aligning the second bond pad and the dummy bond pad of the second semiconductor die with each other; and substantially aligning the fourth bond pad and the electrically isolated region of the first semiconductor die with each other comprises aligning the fourth bond pad and the dummy bond pad of the first semiconductor die with each other.
4. The method of claim 1 , further comprising coupling conductive bond wires to and between conductive pads of the substrate and the conductive elements.
5. The method of claim 1 , wherein aligning further comprises: operably coupling the first and third bond pads located and centered on the respective centerlines of the first semiconductor die and the second semiconductor die to integrated circuitry of both the first semiconductor die and the second semiconductor die; operably coupling the second bond pad over the active surface and offset from the centerline of the first semiconductor die only with the integrated circuitry of the first semiconductor die; and operably coupling the fourth bond pad over the active surface and offset from the centerline of the second semiconductor die only with the integrated circuitry of the second semiconductor die.
6. The method of claim 1 , further comprising physically coupling the second bond pad along the active surface and laterally offset from the centerline of the first semiconductor die with the electrically isolated region of the second semiconductor die using conductive elements.
7. The method of claim 1 , further comprising physically coupling the fourth bond pad along the active surface and laterally offset from the centerline of the second semiconductor die with the electrically isolated region of the first semiconductor die using conductive elements.
8. The method of claim 1 , wherein securing a back side of a first semiconductor die to a substrate comprises securing the back side of the first semiconductor die to one of an interposer substrate, a leadframe, or a circuit board.
9. The method of claim 1 , further comprising providing the first semiconductor die having a size, shape, and configuration and providing the second semiconductor die having substantially the same size, shape, and configuration as the first semiconductor die.
10. The method of claim 1 , further comprising respectively connecting bond wires to the first bond pad located and centered on the centerline of the first semiconductor die.
11. The method of claim 1 , further comprising respectively connecting bond wires to the second bond pad laterally offset from the centerline of the first semiconductor die.
12. A semiconductor device package, comprising: a first semiconductor die and a second semiconductor die, wherein each of the first semiconductor die and the second semiconductor die comprises a centerline defined substantially midway between and parallel to opposing lateral edges of the first semiconductor die and the second semiconductor die, respectively; a first group of conductive elements substantially along the respective centerlines of the first and the second semiconductor dice and operably coupled with integrated circuitry of the first semiconductor die and the second semiconductor die, the first group of conductive elements located equidistant from the opposing lateral edges of the respective first semiconductor die and the second semiconductor die; a second group of conductive elements laterally offset from and on a first side of the centerline and operably coupled with only the integrated circuitry of the first semiconductor die; a third group of conductive elements laterally offset from and on a second side of the centerline opposite the first side and operably coupled with only the integrated circuitry of the second semiconductor die.
13. The semiconductor device package of claim 12 , wherein the conductive elements of the first group, of the second group, and of the third group comprise conductive solder bumps.
14. The semiconductor device package of claim 12 , wherein the first semiconductor die has the same shape, size, and configuration as the second semiconductor die.
15. The semiconductor device package of claim 12 , wherein the second group of conductive elements is arranged along a first line substantially parallel to the centerline and the third group of conductive elements is arranged along a second line substantially parallel to the centerline.
16. A semiconductor device package, comprising: a first semiconductor device comprising an active surface, a first set of bond pads over the active surface and located and centered on a centerline of the first semiconductor device, a second set of bond pads over the active surface and laterally offset from the centerline of the first semiconductor device, and a third set of bond pads over the active surface and laterally offset from the centerline of the first semiconductor device, the centerline of the first semiconductor die defined substantially midway between and parallel to opposing lateral edges of the active surface; a second semiconductor device, comprising an active surface, a fourth set of bond pads over the active surface and located and centered on a centerline of the second semiconductor device, a fifth set of bond pads over the active surface and laterally offset from the centerline of the second semiconductor device, and a sixth set of bond pads over the active surface and laterally offset from the centerline of the second semiconductor device, the centerline of the second semiconductor die defined substantially midway between and parallel to opposing lateral edges of the active surface; a first set of conductive elements each physically and electrically coupled to the first and fourth sets of bond pads along the respective centerlines of the first and second semiconductor devices; a second set of conductive elements each physically coupled to the second and fifth sets of bond pads laterally offset from the centerline of the first and the second semiconductor devices, the second set of conductive elements each electrically coupled only to integrated circuitry of the first semiconductor device through the second set of bond pads; and a third set of conductive elements each physically coupled to the third and sixth sets of bond pads laterally offset from the centerline of the first and the second semiconductor devices, the third set of conductive elements each electrically coupled only to integrated circuitry of the second semiconductor device through the sixth set of bond pads.
17. The semiconductor device package of claim 16 , further comprising a substrate attached to a back side surface of the first semiconductor device, the substrate selected from the group consisting of an interposer substrate, a leadframe, or a circuit board.
18. The semiconductor device package of claim 16 , further comprising a dielectric underfill material between the first semiconductor die and the second semiconductor die and an encapsulant over the first semiconductor die and the second semiconductor die.
19. The semiconductor device package of claim 16 , wherein each of the third and sixth sets of bond pads comprises a dummy bond pad electrically isolated from integrated circuitry of the respective first and second semiconductor die.
20. The semiconductor device package of claim 16 , wherein the second and fifth sets of bond pads are laterally offset from the respective centerline of the first and the second semiconductor devices on a first side of the respective centerline and the third and sixth sets of bond pads are laterally offset from the respective centerline of the first and the second semiconductor devices on a second side opposite the first side of the respective centerline.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 17, 2016
September 25, 2018
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