Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for forming a string of memory cells, the method comprising: forming a source; forming a source select gate material over the source; forming multiple levels of control gate material alternating with multiple insulator levels, the multiple levels of control gate material and multiple insulator levels extending over the source select gate material and over the source; forming respective charge storage structures in the multiple levels of control gate material, forming a first opening through the multiple alternating levels of control gate material and insulator levels, the first opening extending adjacent multiple charge storage structures; forming a semiconductor pillar within the first opening, the semiconductor pillar extending adjacent the multiple charge storage structures adjacent the first opening; removing the semiconductor pillar to expose a sidewall defining the first opening; and forming a vertical semiconductor material along a sidewall of the opening, the vertical semiconductor material coupled to the source, wherein the charge storage structures are separated from the vertical semiconductor material by at least a dielectric material, the vertical semiconductor material having a thickness that is less than a width of the first opening such that a second opening is formed by the vertical semiconductor material.
2. The method of claim 1 further comprising: forming a capping material over the source; and forming the select gate material over the capping material.
3. The method of claim 1 wherein the source comprises one of a metal or a polysilicon.
4. The method of claim 3 wherein the metal is a metal silicide.
5. The method of claim 4 wherein the metal silicide is one of: tungsten silicide (WSi x ), tantalum silicide (TaSi x ), or molybdenum silicide (MoSi x ).
6. The method of claim 3 , wherein the source comprises polysilicon, and further comprising doping the source.
7. The method of claim 6 wherein doping the source comprises one of: doping the source with arsenic or phosphorus to create an n-type conductor or doping the metal silicide source with boron or gallium to create a p-type conductor.
8. The method of claim 1 further comprising at least partially filling the second opening formed by the vertical semiconductor material with an oxide material.
9. The method of claim 1 further comprising forming a conductive plug in a top of the second opening formed by the vertical semiconductor material such that the vertical semiconductor material is coupled to the plug.
10. The method of claim 1 further comprising: forming a drain select gate insulator material over the multiple alternating levels of control gate and insulator materials; and forming a drain select gate conductive material over the drain select gate insulator material; wherein the first opening is formed through and adjacent to the drain select gate insulator material and the drain select gate conductive material, and wherein the vertical semiconductor material is separated from the drain select gate insulator material and the drain select gate conductive material by at least the dielectric material.
11. A method for forming a string of memory cells, the method comprising: forming respective charge storage structures in multiple levels of control gate material, the multiple levels of control gate material alternating with multiple levels of insulator material above a source and a source select gate material; forming a first opening through the multiple alternating levels of control gate and insulator materials, the first opening extending adjacent multiple charge storage structures; forming a semiconductor pillar within the first opening, the semiconductor pillar extending adjacent the multiple charge storage structures adjacent the first opening; removing the semiconductor pillar to expose a sidewall defining the first opening; and forming a monolithic semiconductor liner along a sidewall of the first opening, the monolithic semiconductor liner having an ohmic connection to the source and being adjacent to the charge storage structures wherein the multiple charge storage structures are separated from the monolithic semiconductor liner by a tunnel dielectric, the monolithic semiconductor liner defining a second opening within the liner; forming an insulator material within the second opening; and forming a conductive plug over the insulator material such that the plug connects to a top portion of the monolithic semiconductor liner.
12. The method of claim 11 wherein the source is formed in a material level extending over the substrate; and further comprising: doping the source material; forming a capping material over the source material; forming the source select gate material over the capping material; and forming a drain select gate material over the multiple alternating levels of control gate and insulator material.
13. The method of claim 12 further comprising forming a polysilicon material between the substrate and the source material.
14. The method of claim 12 wherein forming the source select gate material comprises: forming a source select gate oxide over the doped source material; and forming a source select gate conductive material over the source select gate oxide.
15. The method of claim 12 wherein forming the drain select gate material comprises: forming a drain select gate oxide over a top material of the multiple alternating levels of control gate and insulator materials; and forming a drain select gate conductive material over the drain select gate oxide.
16. The method of claim 11 wherein the monolithic semiconductor liner comprises a polysilicon material.
17. A method for forming a string of memory cells, the method comprising: forming a source material over a substrate, including forming an oxide material between the substrate and the source material; doping the source material; forming a capping material over the source material; forming a source select gate material over the capping material; forming respective charge storage structures in multiple levels of control gate material, the multiple levels of control gate material alternating with multiple levels of insulator material, the multiple alternating levels of control gate and insulator materials formed over the source select gate material; forming a drain select gate material over the multiple alternating levels of control gate and insulator material; forming a first opening through the multiple alternating levels of control gate and insulator materials; forming a monolithic semiconductor liner along a sidewall of the first opening, the monolithic semiconductor liner having an ohmic connection to a source material and being adjacent to the charge storage structures wherein the multiple charge storage structures are separated from the monolithic semiconductor liner by a tunnel dielectric, the monolithic semiconductor liner having a thickness that is less than a width of the first opening such that a second opening is formed by the liner; forming an insulator material within the second opening formed by the monolithic semiconductor liner; and forming a conductive plug over the insulator material such that the plug connects to a top portion of the monolithic semiconductor liner.
18. A method for forming a string of memory cells, the method comprising: forming respective charge storage structures in multiple levels of control gate material, the multiple levels of control gate material alternating with multiple levels of insulator material; forming a first opening through the multiple alternating levels of control gate and insulator materials; forming a monolithic semiconductor liner along a sidewall of the first opening, the monolithic semiconductor liner having an ohmic connection to a source material and being adjacent to the charge storage structures wherein the multiple charge storage structures are separated from the monolithic semiconductor liner by a tunnel dielectric, the monolithic semiconductor liner having a thickness that is less than a width of the first opening such that a second opening is formed by the liner; forming an insulator material within the second opening formed by the monolithic semiconductor liner, wherein forming the insulator material comprises, forming an oxide within the second opening and over the drain select gate material; removing the oxide formed over the drain select gate material, and forming a recess in the oxide within the second opening; forming a conductive plug over the insulator material such that the plug connects to a top portion of the monolithic semiconductor liner.
19. The method of claim 18 wherein forming the conductive plug comprises: forming a polysilicon material within the recess and over the drain select gate material; and removing the polysilicon material formed over the drain select gate material while leaving the polysilicon material formed in the recess.
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July 27, 2016
October 2, 2018
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