A voltage converter includes a high side transistor, a low side transistor coupled to the high side transistor at a switching node, and an inductor coupled to the switching node and providing an output node. A controller is provided that is coupled to the high side transistor and the low side transistor. The controller is configured to selectively turn on and off the high and low side transistors in a repeat cycle. The controller is configured to control the high and low side transistors to cause a sequence of packets of charge to be delivered to the inductor. Also included is an adaptive timer circuit coupled to the output node and the controller and configured to adaptively adjust the amount of charge in each packet based on the voltage ripple of the output node.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A voltage converter, comprising: a high side transistor; a low side transistor coupled to the high side transistor at a switching node; an inductor coupled to the switching node; a controller coupled to the high side transistor and to the low side transistor, the controller configured to selectively turn on and off the high side transistor and the low side transistor, to cause the inductor to deliver a sequence of packets of charge to an output capacitor; and an adaptive timer circuit coupled to an output node of the inductor and to the controller, the adaptive timer circuit configured to set a duration of a packet in the sequence of packets based on a duration of a previous packet in the sequence of packets and based on a voltage of the output node.
2. The voltage converter of claim 1 , wherein the controller is further configured to implement a discontinuous/pulse-frequency mode.
3. The voltage converter of claim 1 , wherein the adaptive timer circuit is further configured to set the duration of the packet based on a comparison of the voltage of the output node to a reference voltage.
4. The voltage converter of claim 3 , wherein the adaptive timer circuit is further configured to set the duration of the packet to be longer than the duration of the previous packet, in response to determining that the voltage of the output node is below the reference voltage.
5. The voltage converter of claim 3 , wherein the adaptive timer circuit is further configured to set the duration of the packet to be shorter than the duration of the previous packet in response to determining that the voltage of the output node is above the reference voltage.
6. The voltage converter of claim 5 , further comprising: a zero crossing detection circuit coupled to the switching node and to the adaptive timer circuit, the zero crossing detection circuit configured to assert a signal to the adaptive timer circuit, in response to determining that a drain-to-source voltage of the low side transistor is zero or approximately zero.
7. The voltage converter of claim 1 , wherein the adaptive timer circuit comprises: a comparator configured to determine whether the voltage of the output node is greater than a voltage threshold; an up/down counter coupled to the comparator, the up/down counter configured to: increment the up/down counter, in response to the comparator determining that the voltage of the output node is less than or equal to the voltage threshold; and decrement the up/down counter, in response to the comparator determining that the voltage of the output node is greater than the voltage threshold; and a current control coupled to the up/down counter, the current control configured to output a control current based on the up/down counter.
8. The voltage converter of claim 7 , wherein the adaptive timer circuit further comprises: a time on generator coupled to the current control, the time on generator configured to set a duration of a time on signal based on the current control.
9. The voltage converter of claim 1 , wherein the previous packet immediately precedes the packet.
10. The voltage converter of claim 1 , wherein the voltage converter is a buck converter.
11. A method, comprising: delivering, by a voltage converter, a first packet of electric charge via an inductor to an output capacitor; monitoring, by an adaptive timer circuit of the voltage converter, a magnitude of an output voltage of the voltage converter, after delivering the first packet; selecting, by the adaptive timer circuit of the voltage converter, a duration of a second packet of electrical charge, based on a duration of the first packet and based on the output voltage; and delivering, by the voltage converter, the second packet of electric charge via the inductor to the output capacitor.
12. The method of claim 11 , wherein selecting the duration of the second packet comprises setting the duration of the second packet to be greater than the duration of the first packet, in response to determining that the magnitude of the output voltage is below a voltage threshold.
13. The method of claim 11 , wherein selecting the duration of the second packet comprises setting the duration of the second packet to be less than the duration of the first packet, in response to determining that the magnitude of the output voltage is greater than a voltage threshold.
14. The method of claim 11 , wherein selecting the duration of the second packet comprises: determining whether a voltage of an output node of the voltage converter is greater than a voltage threshold; incrementing an up/down counter, in response to determining that the voltage of the output node is less than or equal to the voltage threshold; decrementing the up/down counter, in response to determining that the voltage of the output node is greater than the voltage threshold; and setting the duration of the second packet based on the up/down counter.
15. The method of claim 11 , further comprising operating in discontinuous/pulse-frequency mode, while delivering the first packet.
16. An adaptive timer circuit, comprising: a comparator, configured to determine whether a voltage of an output node of a voltage converter is greater than a voltage threshold; an up/down counter coupled to the comparator, the up/down counter configured to: increment the up/down counter, in response to the comparator determining that the voltage of the output node is less than or equal to the voltage threshold; and decrement the up/down counter, in response to the comparator determining that the voltage of the output node is greater than the voltage threshold; and a current control coupled to the up/down counter, the current control configured to output a control current based on the up/down counter.
17. The adaptive timer circuit of claim 16 , further comprising: a digital-to-analog converter (DAC) coupled between the up/down counter and the current control, the DAC configured to convert the up/down counter to an analog counter value, the current control configured to output the current control based on the analog counter value.
18. The adaptive timer circuit of claim 16 , further comprising: a time on generator coupled to the current control, the time on generator configured to set a duration of a time on signal based on the current control.
19. The adaptive timer circuit of claim 16 , wherein the adaptive timer circuit further comprises: a disable control coupled to the time on generator and to a controller, the disable control configured to: receive a clock signal from the controller; and output a logic low, in response to receiving the clock signal.
20. The adaptive timer circuit of claim 16 , wherein the time on generator comprises: a first current source configured to generate a current based on an input voltage; a first transistor, a drain of the first transistor coupled to the first current source; a second current source coupled to a gate of the first transistor, the second current source configured to generate a current based on a difference between the input voltage and the voltage of the output node; a second transistor, a drain of the second transistor coupled to the second current source and a gate of the second transistor coupled to a drain of the first transistor; a first switch coupled in parallel with the second current source; a third transistor; a capacitor coupled between a drain of the third transistor and a source of the first transistor; a second switch coupled in parallel with the capacitor; a digital buffer, an input of the digital buffer coupled to the drain of the second transistor; and an AND gate, a first input of the AND gate coupled to an output of the digital buffer and a second input of the AND gate coupled to a disable signal.
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May 19, 2017
October 9, 2018
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