A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of planarizing a substrate surface, comprising: providing a substrate having a major surface of a material layer, wherein the major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate; depositing a polish stop layer on the major surface of the material layer; forming a photoresist pattern on the polish stop layer, wherein the photoresist pattern masks the second region of relatively high removal rate, while exposes at least a portion of the first region with relatively low removal rate; etching away at least a portion of the polish stop layer not covered by the photoresist pattern; and removing the photoresist pattern.
2. The method according to claim 1 , wherein after removing the photoresist pattern, the method further comprises: depositing a cap layer on the polish stop layer and on the material layer; and performing a chemical mechanical polishing (CMP) process to polish the cap layer.
3. The method according to claim 2 , wherein the material layer comprises amorphous silicon.
4. The method according to claim 2 , wherein the CMP process stops on the polish stop layer.
5. The method according to claim 4 , wherein the polish stop layer comprises silicon nitride, and wherein the cap layer comprises silicon oxide or amorphous silicon.
6. The method according to claim 2 , wherein after performing the CMP process to polish the cap layer and the material layer, the method further comprises: performing a dry etching process to etch the polishing stop layer and the material layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 16, 2017
October 16, 2018
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