Phase-change memory device with drive circuit

1. A memory device comprising: an array of memory cells, each memory cell including a phase-change material; a word line coupled to memory cells of the array; a control circuit configured to be controlled so as to operate in a read mode or in a write mode; a first pull-up MOSFET and a second pull-up MOSFET having channels of a first type, the first and second pull-up MOSFETs being connected in series between a first power-supply node configured to be set at a first supply voltage and the word line, the second pull-up MOSFET being arranged between the first pull-up MOSFET and the word line; a first pull-down MOSFET and a second pull-down MOSFET having channels of a second type, the first and second pull-down MOSFETs being connected in series between the word line and a second power-supply node configured to be set at a reference potential, the second pull-down MOSFET being arranged between the first pull-down MOSFET and the word line; and a biasing MOSFET coupled between the word line and a third power-supply node configured to be set at a second supply voltage that is higher than the first supply voltage, wherein the first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than a breakdown voltage of the biasing MOSFET, wherein the control circuit is coupled to the first and the second pull-up MOSFETs, the first pull-down MOSFET, and the biasing MOSFET.

2. The memory device according to claim 1 , wherein each of the first and second pull-up MOSFETs, the first and second pull-down MOSFETs, and the biasing MOSFET is of a fully-depleted silicon-on-insulator (FDSOI) transistor.

3. The memory device according to claim 1 , wherein the first and second pull-down MOSFETs and the first and second pull-up MOSFETs have respective gate-dielectric regions with the same first thickness, and wherein the biasing MOSFET has a gate-dielectric region with a thickness greater than the first thickness.

4. The memory device according to claim 1 , wherein each of the first and second pull-up MOSFETs, the first and second pull-down MOSFETs, and the biasing MOSFET is an enhancement type MOSFET.

5. The memory device according to claim 4 , wherein the first and second pull-up MOSFETs and the biasing MOSFET have channels with P conductivity, and wherein the first and second pull-down MOSFETs have channels with N conductivity.

6. A memory device comprising: an array of memory cells, each memory cell including a phase-change material; a word line coupled to memory cells of the array; a control circuit configured to be controlled so as to operate in a read mode or in a write mode; a first pull-up MOSFET and a second pull-up MOSFET having channels of a first type, the first and second pull-up MOSFETs being connected in series between a first power-supply node configured to be set at a first supply voltage and the word line, the second pull-up MOSFET being arranged between the first pull-up MOSFET and the word line; a first pull-down MOSFET and a second pull-down MOSFET having channels of a second type, the first and second pull-down MOSFETs being connected in series between the word line and a second power-supply node configured to be set at a reference potential, the second pull-down MOSFET being arranged between the first pull-down MOSFET and the word line; and a biasing MOSFET coupled between the word line and a third power-supply node configured to be set at a second supply voltage that is higher than the first supply voltage; wherein the first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than a breakdown voltage of the biasing MOSFET; wherein the control circuit is coupled to the first pull-up MOSFET and the first pull-down MOSFET and is configured to control the first pull-up MOSFET and the first pull-down MOSFET so that they will operate in a state of switching-on allowed and in a state of switching-on forbidden in a way alternating with respect to one another, as a function of an input signal that indicates whether the word line is to be selected or deselected; and wherein, i) when operating in read mode and ii) when operating in write mode with the input signal indicating that the word line is to be deselected, the control circuit is coupled to the biasing MOSFET is configured to control the biasing MOSFET so as to electrically decouple the word line from the third power-supply node and to control the second pull-up MOSFET and the second pull-down MOSFET so that the first pull-up MOSFET and the first pull-down MOSFET are electrically coupled to the word line; and wherein, when operating in write mode and with the input signal indicating that the word line is to be selected, the control circuit is configured to control the biasing MOSFET so as to couple electrically the word line to the third power-supply node and to control the second pull-up MOSFET and the second pull-down MOSFET so that the second pull-up MOSFET is in the state of switching-on forbidden and that the second pull-down MOSFET is in the state of switching-on allowed.

7. The memory device according to claim 6 , wherein the control circuit is configured to set a gate terminal of the second pull-down MOSFET to a cascode voltage, which is higher than a threshold voltage of the second pull-down MOSFET; and wherein, when operating in write mode and with the input signal indicating that the word line is to be selected, the control circuit is further configured to set a gate terminal of the second pull-up MOSFET at a voltage greater than or equal to the difference between the second supply voltage and the modulus of the threshold voltage of the second pull-up MOSFET.

8. The memory device according to claim 7 , wherein the control circuit is configured to generate a first control signal on gate terminals of the first pull-up MOSFET and of the first pull-down MOSFET, and to generate a second control signal, on the gate terminal of the second pull-up MOSFET, wherein the first control signal ranges between the reference potential and the first supply voltage and wherein the second control signal ranges between the reference potential and the second supply voltage.

9. The memory device according to claim 8 , wherein the control circuit is further configured to generate, on a gate terminal of the biasing MOSFET, a third control signal, which ranges between the reference potential and the second supply voltage and is the logic negation of the second control signal.

10. The memory device according to claim 6 , wherein each of the first and second pull-up MOSFETs, the first and second pull-down MOSFETs, and the biasing MOSFET is of a fully-depleted silicon-on-insulator (FDSOI) transistor.

11. The memory device according to claim 6 , wherein the first and second pull-down MOSFETs and the first and second pull-up MOSFETs have respective gate-dielectric regions with the same first thickness, and wherein the biasing MOSFET has a gate-dielectric region with a thickness greater than the first thickness.

12. The memory device according to claim 6 , wherein the biasing MOSFET has a channel of the first type.

13. The memory device according to claim 6 , wherein each of the first and second pull-up MOSFETs, the first and second pull-down MOSFETs, and the biasing MOSFET is an enhancement type MOSFET.

14. The memory device according to claim 13 , wherein the first and second pull-up MOSFETs and the biasing MOSFET have channels with P conductivity, and wherein the first and second pull-down MOSFETs have channels with N conductivity.

15. The memory device according to claim 6 , wherein each memory cell comprises a storage element and an access element, which are electrically coupled together; wherein each storage element is formed by the phase-change material; and wherein each access element is formed by a corresponding MOSFET.

16. An electronic apparatus comprising: the memory device according to claim 6 ; a controller; and a bus electrically coupling the controller and the memory device.

17. A method for biasing a word line of a memory device that comprises an array of phase-change memory cells, wherein the memory device further comprises: a first pull-up MOSFET and a second pull-up MOSFET having channels of a first type, the first and second pull-up MOSFETs being connected in series between a first power-supply node configured to be set at a first supply voltage and the word line and the second pull-up MOSFET being arranged between the first pull-up MOSFET and the word line; a first pull-down MOSFET and a second pull-down MOSFET having channels of a second type, the first and second pull-down MOSFETs being connected in series between the word line and a second power-supply node configured to be set at a reference potential and the second pull-down MOSFET being arranged between the first pull-down MOSFET and the word line; and a biasing MOSFET connected between the word line and a third power-supply node configured to be set at a second supply voltage that is higher than the first supply voltage, the first and second pull-up MOSFETs and the first and second pull-down MOSFETs having breakdown voltages lower than the breakdown voltage of the biasing MOSFET; the method comprising: controlling the first pull-up MOSFET and the first pull-down MOSFET by an input signal that indicates whether the word line is to be selected or deselected, so that they will operate in a state of switching-on allowed and in a state of switching-on forbidden in a way alternating with respect to one another, as a function of the input signal; during a reading step, and during a writing step with the input signal indicating that the word line is to be deselected, controlling the biasing MOSFET so as to decouple electrically the word line from the third power-supply node, and controlling the second pull-up MOSFET and the second pull-down MOSFET so that the first pull-up MOSFET and the first pull-down MOSFET are electrically coupled to the word line; and during a writing step with the input signal indicating that the word line is to be selected, controlling the biasing MOSFET so as to couple electrically the word line to the third power-supply node, and controlling the second pull-up MOSFET and the second pull-down MOSFET so that the second pull-up MOSFET is in the state of switching-on forbidden and the second pull-down MOSFET is in the state of switching-on allowed.

18. The method of biasing according to claim 17 , further comprising: setting a gate terminal of the second pull-down MOSFET at a cascode voltage, which is higher than a threshold voltage of the second pull-down MOSFET; and during the writing step with the input signal indicating that the word line is to be selected, setting the gate terminal of the second pull-up MOSFET at a voltage higher than or equal to the difference between the second supply voltage and the modulus of a threshold voltage of the second pull-up MOSFET.

19. The method of biasing according to claim 18 , further comprising: generating a first control signal on gate terminals of the first pull-up MOSFET and of the first pull-down MOSFET, wherein the first control signal ranges between the reference potential and the first supply voltage; and generating a second control signal on the gate terminal of the second pull-up MOSFET, wherein the second control signal ranges between the reference potential and the second supply voltage.

20. The method of biasing according to claim 19 , further comprising generating, on a gate terminal of the biasing MOSFET, a third control signal, which ranges between the reference potential and the second supply voltage and is the logic negation of the second control signal.